[Table of Contents]
The microSPARC 32-bit microprocessor is a highly integrated RISC CPU Implementing the SPARC Architecture ver.8. Due to its relative high performance and low cost, it is ideally suited for low-cost single processor applications.
The microSPARC includes: A pipelined Integer Unit (IU), a Floating Point Unit (FPU), separate Instruction and Data Caches and a fully implemented Reference MMU.
It interfaces efficiently with the rest of the system, by incorporating complete DRAM and SBus interface and controllers. Testability at the system level is provided by supporting a complete JTAG interface.
Operating at the nominal internal frequency of 50 MHz, the throughput achieved is 26 SPECint92 and 21 SPECfp92.
- SPARC High Performance RISC architecture
- Operating Frequency at 50 MHz
- 7 window, 120-word register file
- 4 Kbyte Instruction cache, 2 Kbyte Data cache
- On-chip Memory Management Unit
- Integrated Floating Point Processor
- Interface to S-Bus at 1/2 system clock
- Integrated DRAM controller
- IEEE1149.1 (JTAG) boundary scan test bus
- TAB Packaging
- Compatible with 7500 SPARC applications and development tools
- 50 MIPs peak performance
- Fast interrupt response, procedure calls and program execution
- Decouples processor operation from slow external memory
- Support for sophisticated operating systems with memory protection and virtual addressing
- 12 MFlops peak performance
- Connection to industry standard expansion bus
- Simple, low part count system design
- Ease of manufacturing test
- Low cost, high density board assembly
- file last updated 14 Nov, 1995 -
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