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ATM Segmentation and Reassembly (SAR) Processors


WAC-020: AAL5 SAR (AALVin™) Processor

WAC-021: AAL1 SAR (AAL1gator™) Processor Software Driver

WAC-035: Switched Ethernet SAR (SESARTM) Processor

WAC-121: AAL1 SAR (AAL1gator II TM) Processor with SRTS


WAC-020

AAL5 SAR (AALVin™) Processor
Description

The ATM Adaptation Layer Five (AAL5) Segmentation And Reassembly (SAR) Processor (AALVin™) provides ATM layer functions, along with a flexible Universal Test and Operations PHY Interface for ATM (UTOPIA) interface. The AAL5 SAR Processor delivers an integrated solution for performing the SAR tasks required to communicate over an ATM network. The SAR tasks include segmentation and reassembly of AAL5 packet data, and shaping transmit data to a variety of different traffic types (for example, CBR, VBR, and ABR). The device translates packet-based data into 53-byte ATM cells and is ideally suited for equipment requiring an interface between packet-based data and ATM-based networks, such as ATM adapters, ATM switches, hubs, bridges, routers, and test equipment. IgT also offers the AAL5 SAR Processor Device Control Package (WAC-020-DCP) for the AAL5 SAR Processor.

For documentation on the WAC-020 click here.


WAC-021

AAL1 SAR (AAL1gatorTM) Processor
Description

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gatorTM) provides DS1 or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. IgT also provides a software driver (WAC-021-DRV) for the WAC-021.

For documentation on the WAC-021, click here.

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WAC-035

Switched Ethernet SAR (SESARTM) Processor
Description

The Switched Ethernet Segmentation And Reassembly (SESARTM) Processor (WAC-035) provides a flexible, upgradeable solution for performing the Ethernet switching and SAR tasks required to communicate over an ATM network. The SESAR Processor accepts packets directly from Ethernet Medium Access Control (MAC) chips, and then translates the packet-based data into 53-byte ATM cells. It is ideally suited for producing ATM-ready Ethernet switching hubs, bridges, and routers; adding ATM ports to a packet switch; and, providing a high performance Broadcast and Unknown Server (BUS) for an ATM switch. IgT also offers a software driver (WAC-035-DRV) for the SESAR Processor.

For documentation on the WAC-035, click here.

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WAC-121

AAL1 SAR (AAL1gator II TM) Processor with SRTS
Description

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II TM) provides DS1, E1, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. IgT also offers a device control package (WAC-121-DCP) for the AAL1gator.

For documentation on the WAC-121, click here.


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