VAutomation Incorporated 
  The V8-microRISC is an tiny 8-bit RISC cpu ideal for embedded applications


8-bit RISC CPU that is fully synchronous and synthesizable in either VHDL or Verilog
The V8-uRISCTM 8-bit RISC microprocessor is a general purpose, synthesizable processor core designed specifically to be embedded in both ASICs and FPGAs. The V8-uRISC and its available peripherals allow true system-on-chip integration using ANY ASIC or FPGA technology. Supplied with a comprehensive set of support tools, the V8-uRISC will reduce your development cost and risk while speeding your product to market.

High Performance and Low Power
The V8 is ideal for System-on-Chip embedded applications as a synthesizable CPU core available in either vhdl or verilog The V8-uRISCTM combines a small gate count with single clock cycle execution for many instructions to deliver a high performance 8-bit microprocessor with a very small footprint. The V8-uRISC is ideal for 8-bit applications which need a combination of small size, good performance and low power.

Small Size Yields SOC Integration
Although the small size of the V8-uRISCTMis an enabler for system-on-chip (SOC) integration using any ASIC or FPGA technology, it is especially well suited for FPGA applications. The V8-uRISC along with several peripherals can be implemented in an FPGA priced in volume under $10. The result is a low-cost microcontroller customized for your application.

Robust Set of Peripherals
The V8-uRISCTM is delivered with a set of standard peripherals including a counter/timer, UART, and a power-save unit, I2C EEPROM interface, P1284 parallel interface, SPI and page register design to expand the address space to 8 megabytes. Optional Universal Serial Bus and IEEE 1394 (FireWire) Serial Bus interfaces are also available.

Technology Independent and Customizable
Delivered in either VHDL or Verilog synthesizable source form, the V8-uRISC is both technology independent and user-customizable. Your ASIC or FPGA synthesis tool can target the V8-uRISC to the process/library of your choice. During this targeting step the synthesis tool can perform architecture specific optimizations that would be impossible to do if only a netlist were supplied. Additionally, the availability of source code allows custom opcodes to be added for improved throughput at a lower clock frequency.

Robust Set of Software Development Tools
The V8-uRISC is supported by a complete set of development tools for every stage of software development. A full ANSII C compiler, developed by HiTech Software, assembler, software simulator, debugger and an FPGA based development system (Intellicore Prototyping System) are available for rapid software development and testing. JTAG debugger screen shot for the V8 synthesizable 8-bit microprocessor core

The software simulator is a Win32 application that loads and executes an Intel hex file. It provides a high speed debugging interface for quickly debugging V8-uRISC software and allows software debug to begin before the V8 has been realized in silicon.

In-system debugging is accomplished via a JTAG-based debugger that requires only 4 pins on the final silicon implementation. The JTAG debugger uses one IPS as a JTAG master to communicate to a PC via a standard serial port. The PC hosts a Win 32 application that provides the debugger interface. The IPS is then connected via the 4 JTAG pins to a JTAG Test Access Port (TAP) or "slave" controller that is an optional peripheral to the V8-uRISC. The JTAG slave controller and V8 can be implemented in an IPS being used as an FPGA emulation of the target chip prior to first silicon. (insert diagram showing PC, JTAG master and IPS/Silicon here)

The JTAG slave controller requires approximately 3,000 gates and provides sufficient logic to stop, single-step, set a single breakpoint, and read or write to memory. This level of functionality is small enough to be included in FPGAs or early ASIC runs. Typically the JTAG slave controller is removed when the chip has entered full volume production and the software is completely stable.

The PC debugger interface allows the user to control the execution of the V8-uRISC and displays the executed assembly and C code, program counter, register values and memory contents. The following operations can be performed:

  • Start/stop/reset processor
  • Execute one clock, instruction, subroutine or C statement
  • Breakpoint on specified bus activity
  • Download a program
  • Examine/change program counter
  • Examine/change register values
  • Examine/change RAM
The V8's biggest feature is it's very low gate count for an synthesizable 8-bit microprocessor core
Under 3,000 Gates for the base CPU
  Ideal processor for cost sensitive embedded applications
  1883 gates + 16x8 Register file in LSI Logic G10, 79MHz area optimized, prelayout
  268 Xilinx XC4000 CLBs, 16MHz postlayout in a XC4013e-1
RISC architecture for low gate count and high performance
  Single Cycle instruction execution for all register to register opcodes
  16Mhz operation in many FPGA families
  100 Mhz operation in 0.35um CMOS
High Code density, many opcode are a single byte
ASIC/FPGA Vendor Independent, Technology Independent
  Available in either VHDL or Verilog
  Fully synchronous and static design
33 opcodes, 4 addressing modes, 2 user defined opcodes
  Custom opcodes for 1024 bit math, table lookups, DSP functions are easily added
8-bit ALU
64K byte addressing capability
Eight 8-bit General Purpose Registers
  Multiple register banks are easily implemented to minimize interrupt latency
16-bit Program Counter and Stack Pointer
Seven maskable interrupts, one non-maskable
Robust Software Development Tools
  ANSII C compiler from HiTech Software
  JTAG C or Assembly Source Level Debugger
  Customizable Assembler in ANSI C source code included
  128 BIST ROM assembly source code
  IntelliCoreTM Prototyping System available for evaluation and rapid product development
FREE Assembler/Debugger/Simulator available for immediate download 


VAutomations Synthesizable Cores are ideal for .35um, .25um or even .18um CMOS and are available in either VHDL or Verilog
V8-uRISC Synthesizable VHDL or Verilog Source Code
V8-uRISC Peripherals Synthesizable VHDL or Verilog Source Code
  16-bit Counter/Timer
  UART
  Power-Save Unit
  P1284 PC Parallel Port interface
  IEEE 1149 JTAG slave controller
  SPI serial bus interface
Behavioral Testbench implementing the IntelliCoreTM Prototyping System
V8-uRISC assembler ANSI C Source code
V8-uRISC Instruction Set Simulator for Windows95
V8-uRISC JTAG Debugger for Windows95
Sample Synthesis Scripts


Optional Peripherals
VUSB Universal Serial Bus Target/Hub
V1394 IEEE 1394 High Performance Serial Bus (FireWire) (Q2 1999)




Request detailed Documentation on the V8-uRISC


V8-uRISC is a trademark of VAutomation, Inc.

info@vautomation.com

Programming Model
The V8-uRISCTM CPU is a Von Neuman architecture which provides a single address space for both code and data. The 64K byte address space can be divided easily between RAM, ROM or hardware IO registers. Blocks of the address space can also be used to provide windows into "banked" memory which can extend the address space to virtually any size.

The register file is usually implemented as a dual-port RAM to minimize the size. Typically two banks of registers are provided, one for regular processing and another bank for interrupt processing. Interrupt service times are dramtically reduced in this scheme as registers do not have to be pushed onto the stack.

The V8-uRISCTM uses eight 8-bit registers to perform all arithmetic and logical operations. Register Zero (R0) can be thought of as an accumulator as it is typically one of the source operands and the destination register for the opcode. Registers R1 through R7 are general purpose. Register pairs can be used as sixteen bit index registers for addressing memory.


Eight 8-bit General Purpose Registers
7 6 5 4 3 2 1 0
R0
Accumulator
R1
R2
R3
R4
R5
R6
R7

The Program Status Register (PSR) is updated by many opcodes and all 8 bits can be tested by the relative branch opcodes.

Program Status Register
bit # Description
PSR[7] General Purpose bit
PSR[6] General Purpose bit
PSR[5] General Purpose bit
PSR[4] General Purpose bit
PSR[3] Interrupt Enable
PSR[2] Negative Flag
PSR[1] Carry Flag
PSR[0] Zero Flag

Full sixteen bit counters are used for the Program Counter (PC) and Stack Pointer (SP). Some gates can be saved by reducing the size of these registers in very cost sensitive applications.

16-bit Progam Counter and Stack Pointer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Program Counter
PC
Stack Pointer 
SP


Instruction Set Overview
The V8-uRISCTM instruction set is small and compact to provide maximum code density and high throughput. All register to register opcodes are a single byte as well as indexed memory accesses. Branch opcodes are two bytes and some memory access opcodes are three bytes.

Opcode Format
7 6 5 4 3 2 1 0   7 6 5 4 3 2 1 0   7 6 5 4 3 2 1 0
Opcode REG
Opcode REG   Byte1
Opcode REG   Byte1   Byte2

The V8-uRISCTM opcodes provide all of the power required to implement any cost sensitive embedded application. Bit-Testing opcodes as well as the usual Arithetic/Logical/Shift opcodes are provided. Relative branches require only two bytes. All of the register to register opcodes require only a single clock to execute.

The two User Defined opcodes can be used to implement any application specific function. Analysis of your application code can typically identify one or two functions that require most of the CPU bandwidth. By coding these functions as a single opcode, performance can be significantly increased without increasing the clock rate. This in turn can keep the power requirements of your product low. Typically applications include 512 or 1024 bit math for high speed Public Key Encryption algorthims, Multiply/accumulate for DSP application, Table lookups for decoding or Trigonometric functions commonly used in handheld GPS devices, Block moves, etc.


Opcode Map
MSB/LSB 000 001 010 011 100 101 110 111
00 INC ADC TX0 OR AND XOR ROL ROR
01 DEC SBC ADD STP BTT CLP T0X CMP
10 PSH POP BR0 BR1 USR INT USR2 JMP*
11 UPP STA STX STO LDI LDA LDX LDO

Note: the JMP opcode includes JMP, JSR, RTS and RTI opcodes. The REG field is decoded to differentiate between these opcodes.

Opcode Details
Opcode
in Hex		 Assembler
Notation		 Operand Clock
cycles		 PSR Description
00 INC Rn 1 NCZ Rn=Rn+1
08 ADC Rn 1 NCZ R0=R0+Rn+C
10 TX0 Rn 1 NZ R0=Rn
18 OR Rn 1 NZ R0=R0|Rn
20 AND Rn 1 NZ R0=R0&Rn
28 XOR Rn 1 NZ R0=R0^Rn
30 ROL Rn 1 NZC Rn={Rn<<1,C}
38 ROR Rn 1 NZC Rn={C,Rn>>1}
40 DEC Rn 1 NCZ Rn=Rn-1
48 SBC Rn 1 NZC R0=R0-Rn-C
50 ADD Rn 1 NZC R0=R0+Rn
58 STP # 1 * PSR[#]=1, Set bit in PSR
60 BTT # 1 NZ Bit Test; if R0[#]=0, Set Z else clear Z
68 CLP # 1 * PSR[#]=0, Clear bit in PSR
70 T0X Rn 1 NZ Rn=R0, Transfer
78 CMP Rn 1 NZC R0-Rn, Compare
80 PSH Rn 3 Push Rn on STACK
88 POP Rn 3 Pop STACK to Rn
90 BR0 #,offset 3 Relative branch if PSR[#]=0
98 BR1 #,offset 3 Relative branch if PSR[#]=1
A0 USR User Defined Opcode (NOP by default)
A8 INT # 7 I=1 Interrupt
B0 USR2 User Defined Opcode (NOP by default)
B8 RSP 5 Reset Stack Pointer
B9 RTS 5 Return from Subroutine
BA RTI 5 stack Return from Interrupt
BB BRK 5 Reserved for debugging. Performs a 5 clock NOP
BC JMP 16 bit addr 3 Jump to addr
BF JSR 16 bit addr 5 Jump to Subroutine addr
C0 UPP Rn 2 C Increment Register Pair
C8 STA Rn,addr 4 Store Rn to addr
D0 STX Rn 3 Store R0 indexed MEM{Rn+1,Rn}=R0
D8 STO Rn, offset 4 Store R0 Indexed with offset MEM{Rn+1,Rn}+offset=R0
E0 LDI Rn, value 2 NZ Load Rn Immediate
E8 LDA Rn,addr 4 NZ Load Rn from addr
F0 LDX Rn 3 NZ Load R0 Indexed R0=MEM({Rn+1,Rn})
F8 LDO Rn, offset 4 NZ Load R0 Indexed with offset R0=MEM({Rn+1,Rn}+offset)

IO Signal List
Pin Name Direction Description
ADDR[15:0] OUT Address Bus
DATAIN[7:0] IN Data Input Bus
DATAOUT[7:0] OUT Data Output Bus
READ OUT Read Cycle - High when data is being loaded from the DATAIN bus.
WRITE OUT Write Cycle - High when data is valid on the DATAOUT bus.
CLK IN Clock - All Flip-Flops clock on the rising edge of the clock.
RESET IN Reset - Must be asserted for at least 3 rising edges of CLK.
INT[7:0] IN Interrupt Request - INT[0] is Non-maskable and is generally reserved for JTAG debugging purposes.
READY IN Ready - Freezes the current state when low, operation completes when high. Must be high when RESET is asserted.
OP_FETCH OUT Opcode Fetch Cycle. Typically used for single step debugging.
CLR_P[7:4] IN Clear PSR bit
SET_P[7:4] IN SET PSR bit
PSR OUT Program Status Register