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ArticlesAligning Instructions for Multiple Dispatch

September 1994 / Features / Aligning Instructions for Multiple Dispatch

The R8000's instruction buffer is a FIFO (first-in/first-out) queue in which each entry is a quadword (i.e., 128 bits) containing four instructions read from the instruction cache. The last entry in this queue is made visible via a set of four 32-bit registers called the on-deck registers, which feed another set of four dispatch registers. The latter are equivalent to the instruction register of a conventional single-issue microprocessor and connect to the decode logic and the register file. The figure at right shows four cycles of the buffer operation with individual instructions represented by letters of the alphabet. The cycles are explained below.

Cycle 1: Instruction C depends on the result of A, so the dispatch logic decides that only instructions A and B can be issued in pa rallel (as D must not be issued out of order).

Cycle 2: A and B are dispatched for execution, E and F move from the on-deck registers to replace them, and the program counter points to C.

Cycle 3: C, D, and E are dispatched in parallel and are replaced by G and H (from the on-deck registers) and I, which bypasses the on-deck registers. The emptying of the on-deck registers triggers a buffer advance on the next cycle.

Cycle 4: The buffer advances one line and reads four more instructions from the cache. F and G are dispatched.

The overall effect of this mechanism is to provide a continuous stream of aligned instructions for execution. Meanwhile, the dispatch-decision logic has to manipulate only the four dispatch registers and is not burdened with the whole instruction-fetch pipeline.

Figure: Unaligned Dispatching

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