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  • 32-bit R3000-class embedded processor core
  • Operates at 33 MHz in an EPF10K200E or larger device
  • Supports MIPS1 instruction set architecture (see note 1 below)
  • Supports MIPS16 code compression
  • Includes an optional Multiply-Accumulate (MAC) engine
  • Includes optional EJTAG on-chip software debug functionality
  • Supported by industry standard development tools and real-time operating systems
  • Evaluation system board available

Block Diagram

Figure 1. shows the block diagram for the LX4180 megafunction.

Figure 1. Block Diagram
Figure 1. Block Diagram

General Description

The LX4180 is a 32-bit reduced instruction set computer (RISC) processor which executes the MIPSI instruction set (see Note 1 below). It allows designers to take advantage of a wide array of software development tools available from commercial suppliers.

The LX4180 can be configured to execute MIPS16 compressed code. Multiplication and division operations can be performed in hardware by a configurable MAC engine. On-chip code debug can be performed on the LX4180 with the configurable EJTAG block.

Architecture Overview

The LX4180 megafunction is based on Lexra's high-performance LX4180 embedded processor architecture.  Following are characteristics of the LX4180 CPU:

Table 1. Architectural Features of the LX4180 Function
Feature Description
MIPSI Instruction Set Architecture (1) The LX4180 supports the MIPSI programming model. The instruction set incorporates a three-port register file. Two source operands can be supplied and one destination updated per cycle. The second operand is either a register or 16-bit immediate. The instruction set includes a wide selection of arithmetic logic unit (ALU) operations executed by the register arithmetic logic unit (RALU), Lexra's proprietary register-based ALU. The RALU also generates memory addresses for 8-bit, 16-bit and 32-bit register loads from and stores to memory by adding a register base to an immediate offset. Branches are based on comparisons between registers, rather than flags, and are therefore easy to relocate. Optional links following jump or branch instructions assist with subroutine programming.
Pipeline Instructions are executed by a five-stage pipeline. The pipeline is designed so that all internal transactions and interfaces occur on the positive edge of the processor clock. Two-phase clocks are not used.
Exception Handling The LX4180 supports the MIPSI exception handling model. Exceptions include instruction-synchronous traps, hardware, and software interrupts. All exceptions are prioritized. When an exception is taken, control is transferred to a user program located at the exception vector. The use program identifies the cause of the exception and transfers control to the application-specific handler.
Co-processor Operations The LX4180 supports all 32-bit co-processor operations. These include moves to and from the co-processor general registers and control registers (MTCz, MFCz, CTCz, CFCz), co-processor loads and stores (LWCz, SWCz) and branches based on co-processor condition flags (BCzT, BCzF). The LX4180 includes a co-processor interface which can support all co-processor operations in a single cycle, without pipeline stalls.

In addition to the LX4180 CPU, the LX4180 megafunction includes the following standard blocks:

  • The Simple Memory Management Unit (SMUU) is designed for embedded applications that use a single address space. Its primary function is to provide memory protection between user space and kernel space.
  • Two Local Memory Interfaces (LMI). One local memory interfaces to 2 Kbytes of instruction memory and the other interfaces to 2 Kbytes of data memory.
  • The Coprocessor Interface (CI). The co-processor interface "eavesdrops" on the instruction. If a co-processor load (LWCz) or move to (MTCz, CTCz) is decoded, data will be enabled from the data bus into a CI register, then supplied to the designer-defined co-processor. Similarly, if a co-processor store (SWCz) or move from (MFCz, CFCz) is decoded, data will be fetched from the co-processor and loaded into a CI register, then transferred onto the data bus in the following cycle. The design interface includes a variable-width data bus, five-bit address and independent read and write selects for co-processor register and registers. The LX4180 pipeline and Harvard architecture permit single cycle co-processor access and transfer. Designer-defined co--processor condition flags (CpCondz) are synchronized by the CI then passed to the sequencer for testing in branch instructions.
  • The Custom Engine Interface (CEI), which the designer can use to extend the MIPS ALU opcodes with application-specific or proprietary operations. Similar to the standard ALU, the CEI supplies the custom engine with two input 32-bit operands, SRC1 and SRC2. One operand is selected from the register file. Depending on the opcode, the second operand is either selected from the register file or is a 16-bit sign-extended immediate. The opcode is locally decoded by the custom engine and, following execution by the custom engine, the result is returned on the 32-bit RES bus to the LX4180.

The LX4180 can be configured with the following optional features:

  • The Lexra Bus Controller (LBC) connects peripheral functions and secondary memories to the processor's own local buses. It is a multiplexed, no-pipelined, and non-parity-checked bus that provides the easiest protocol for design integration. On the processor side, the LBC provides a four word deep write buffer, and control for byte and half-word transfers. On the peripheral side, the LBC is designed to interface easily with industry standard bus protocols, such as peripheral component interconnect (PCI), universal serial bus (USB) and IEE Std. 1394.
  • MIPS16 instruction compression reduces program size by up to 40%. On-chip programs require less memory, resulting in cost saving for system-on-chip designs.
  • The optional MAC engine completes one multiple or divide instruction every cycle, for performance in signal processing applications.
  • The LX4180 implements the industry standard EJTAG 2.0.0 specification for full-speed debug with real time instruction trace.
  • Software Tool Support: The LX4180 is supported by development tools from Green Hills Software Inc., Wind River Systems, and Embedded Performance Inc.

Device Utilization Example

Table 2 lists the typical device utilization results for the megafunction.

Table 2. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance
Parameter Setting
Logic Cells EABs/ESBs (1)
- 4,000 - 12,000 2 - 200 33 MHz Contact Lexra


  1. EABs: Embedded array blocks, ESBs: Embedded system blocks

Additional Information

The following items are available with the LX4180 megafunction:

  • Netlist file for use with the MAX+PLUS® II software
  • Encrypted register transfer level (RTL) model for simulation model
  • Encrypted register transfer level (RTL) model for simulation with industry standard simulators
  • Lexra Regression Test Kit
  • Optional: LX4x80 Evaluation System Board


  1. Unaligned load and store instructions are not supported in hardware. MIPS, R3000, MIPS common-law marks are trademarks or registered trademarks of MIPS Technologies, Inc. Lexra, Inc. is not associated with MIPS Technologies, Inc. in any way.

Contact Information

For additional information, contact Lexra at:

Lexra Incorporated
2055 Gateway Place, Suite 150
San Jose, CA 95110
Tel: (408) 573-1890
Fax: (408) 573-1898
E-mail: info@lexra.com
WWW: http://www.lexra.com