Special: Ten myths of SLAs Active Directory XML

News    Products   Community   Webcasts   Expert  Advice   Newsletters     Membership
ITcareers   Product Finder   RFP Exchange    White Papers   Training     Marketplace

Search   Browse
Free Newsletter!
ITworld.com this week
More Newsletters
Computers and Peripherals News

Update: Microsoft warns of serious Windows 2000 hole

Hacker's appeal hinges on interpretations of fair use doctrines

HP releases high-speed Internet printer

Apple launches thinner, lighter iBook

Microsoft admits flaw in Windows 2000 server software

Latest ITnews
May 2, 2001

Update: Microsoft warns of serious Windows 2000 hole

Hacker's appeal hinges on interpretations of fair use doctrines
May 1

Senators propose e-government bill
May 1

Citigroup, Microsoft offer online money-transfer system
May 1

AOL, Microsoft heading for instant messaging showdown
May 1

Study: EU privacy directive would cost US consumers
May 1

HP releases high-speed Internet printer
May 1

Best Buy buys into AT&T's INCS
May 1

Apple launches thinner, lighter iBook
May 1

Microsoft admits flaw in Windows 2000 server software
May 1

Computers and Peripherals

Home    Computers and Peripherals    Computer Architecture    Processor architecture    Data buses 

 Printer Friendly Format
 Mail to a friend
 On this topic
 Discuss IT hardware problems and solutions
 ASP Tutor. Sign up Now!
 Other articles
 Rambus, Infineon go head-to-head
 Related Jobs
 Search our jobs database for the top jobs involving computers and peripherals.
 Vendor White Papers
 Computer Architectures
Buses: Front-side and backside
Computerworld 4/30/01

Buses are hardware paths that link a computer's microprocessor with memory chips and devices it communicates with. A front-side bus connects the CPU to main memory and to peripheral buses that run to such system components as disk drives, modems and network cards. A backside bus is a relatively high-speed link that the CPU uses to pass information to and from external cache memory, most often the Level 2 cache. Buses are frequently described by their speed, expressed in megahertz.

Alan Joch, Computerworld

Drop a 450-horsepower, 10-cylinder Dodge Viper engine into your vintage Yugo, and you'll have the hottest wheels this side of Bosnia, right? Maybe, unless the transmission melts down, the axles crumble and the body panels fly off like a barn roof in a tornado.


In just the same way, savvy computer users know that merely plugging a top-end microprocessor into an untuned computer system doesn't guarantee a satisfying improvement in overall performance. And venturing farther under the hood, the speed and efficiency of the CPU itself depends to a considerable degree on the front-side bus that engineers have designed into the processing chip set, as the CPU and other chips associated with it are known.

An essential aspect of the CPU's actual performance is the speed of the front-side bus, the main pipeline a CPU uses to communicate with the rest of the system. Today's front-side buses, like the 400-MHz conduit in the Pentium 4, shuttle data back and forth at a rate more than three times faster than the Pentium III's 133-MHz front-side bus.

By contrast, the backside bus, which confines itself to handling cache data, actually runs at the clock speed of the CPU. In ancient times (circa the mid-1990s), the backside bus was an important way to keep data on the move. Intel Corp.'s Pentium II and Pentium Pro both used a so-called off-chip cache, which held frequently used data nearer (in both distance and the time needed to access it) to the main processing unit than data that was held in conventional memory. A wire bonding linked the CPU to this Level 2 (L2) cache resource and shuttled data between the two destinations at the clock rate of the CPU. Intel's rivals, like Advanced Micro Devices Inc. in Sunnyvale, Calif., soon began using the same tactic.

On- and Off-Chip

There were trade-offs in an off-chip cache design, however. The cost of producing a two-chip set was higher than single-chip designs, and the two separate elements took up precious real estate on the motherboard. In addition, the first Pentium systems to use the backside bus arrangement came with custom -- and very expensive -- static RAM for the cache.

More recently, microprocessor engineers have taken the next logical step in CPU-to-cache communications: they have integrated the L2 cache into the CPU's own silicon substrate. This shrinks the real estate requirements of the processing unit, cuts packaging costs and allows designers to move to lower-priced pipeline burst static RAM. Rather than needing an external wire to connect CPU and memory, chip designers could now incorporate the backside bus in silicon.

"Almost all mainstream processors have now put the second-levvel cache on the chip," says Kevin Krewell, an analyst at Micro Design Resources, a publisher and consulting firm in Sunnyvale, Calif., that specializes in chip design trends. "The backside bus is now on the chip die; it's not exactly a bus any longer."

But the days of the discrete backside bus aren't entirely over. The 400- and 500-MHz PowerPC G4 processors that power Apple Computer Inc.'s Power Mac G4, Cube and Titanium notebook, for example, continue to rely on a backside bus design. The G4 processing engine uses a 1MB backside L2 cache on the processor and a 64-bit backside bus that partners with a 100-MHz front-side bus to achieve a rated data throughput maximum of 800M bit/sec.

Intel and Compaq Computer Corp. haven't forsaken the backside bus, either. Advanced chips that provide a Level 3 cache include Intel's 64-bit Itanium processor and Compaq's Alpha EV8, both of which will continue to use this bus design to keep data flowing.

In addition, separate caches open the way for more efficient multiprocessing in PCs or servers that have more than one processor. If each processor didn't have its own cache reserve, it would have to share a central memory pool with its CPU mates, and that would reduce overall system performance as the processors contend to divvy up a precious resource.

"Everybody recognized this is a better solution than using a front-side bus," Krewell says. "To share bandwidth with system memory is nonoptimal."

Now if only that Yugo could get its backside in gear.

Alan Joch is a freelance writer specializing in technology and business topics. His work appears in Fortune Small Business, Network Magazine, Healthcare Informatics, and other publications.

Sponsored links
Become an Oracle Certified Professional
A digital generation. WorldCom(sm), generation d.
May 2 is Global Speech Day. FIRST-OF-ITS-KIND Web event about speech recognition. Register today!
LeadersOnline-your IT career agent. We bring exclusive opportunities to you!
Buy Red Hat Linux with IBM Software & receive a Red Hat Network- free trial.
RFP Exchange: Fast & Efficient way to contact E-business providers NOW!
Component Registry - a database of JavaBeans, COM components and more.
Think you know everything, IT Guru � Is that your final answer?
Product Finder - Reduce the time it takes you to research IT solutions.

Application Development | Applications | Careers | Computers & Peripherals | IT Management | Networks | Security | Technology in Business
News | Products | Community | Webcasts | Expert Advice | Newsletters | Membership


ITcareers | Product Finder | RFP Exchange | White Papers | Training | Marketplace
About Us | Advertising Info | Links, Reprints, & Permissions | Privacy Policy | Terms of Service | Copyright | Customer Service