Hardware specifications for DNARD (Revision 5)
The table below gives pointers to the drawings for each page of the schematic.
There is also a single PDF document with the entire schematic
There is a list of changes made between rev 4 and rev 5.
As a result of building 1800 boards we have some recommended changes (not shown on the schematic), these are described on the changes page, last updated 15 Sept 97.
Thanks to the manufacturers of the major chips for allowing us to put copies of their data sheets locally on this web site. As always, check with the chip vendors for the latest information!
- The page name points to notes for that page.
- Local signals are declared per page (pascal-like syntax).
- The PS and PDF links point to the schematic for that page in PostScript and PDF.
- The datasheet links cover the main devices on that page, and additional useful information.
- Package pinout information for many parts was extracted from the CAD models and is presented on a separate page.
Schematic Data Sheet/notes Signals/drawing Toplevel Bus definitions
CPU and PAL
StrongARM SA-110 datasheet
SA110 instruction timing note
MACH 231-6 datasheet
IDT74FCT164245 3V to 5V 16-Bit Translating Transceiver
Pal source - Commented source for simulator/MACXL extraction. REV5 defined
Pal equations Rev 4 and 5 - extracted MACXL
Simulation timing diagrams for PAL
74ACT00 Quad 2-Input NAND Gate
74LVC04 Hex Inverter, any reasonable speed 3.3V with 5V tolerant inputs should work (eg LCX parts)
Also: 14.31818MHz osc module
Samsung KMM366S104BTN SDRAM DIMM
74FCT3573 3.3V Octal Transparent Latch
74FCT3574 3.3V Octal D Register w/3-State
74FCT163501 3.3V 18-Bit Bidirectional Buffer/Latch/Register
74LVC257 Quad 2-Input Multiplexer, any fast 3.3V version should work, the outputs are always enabled so the xx157 should work too
CyberPro 2010 datasheet rev 1f
CyberPro 2010 programmer guide rev 1f
CyberPro 2010 Layout Application Note rev 1a
15 pin VGA connector
EtronTech EM61463A-35 256Kx16 DRAM is recommended by IGS
Mosel Vitelic V53C16258H-35 256Kx16 DRAM is an alternative
IGS recommends use of the -35 parts, slower ones may work.
Clocks and ROM card
54/74FCT388915T 8 Output PLL Clock Generator w/3-State 70/100/133/150MHz
74FCT16245 16-Bit Buffered Transceiver
74FCT16244 16-Bit Buffer
74FCT827 10-Bit Buffer
74ACT74 Dual D Flip-Flop
C4069 CMOS hex inverter
Also: 33MHz osc module
74FCT16244 16-Bit Buffer
Amd29F040 Flash memory
IDE interface description
I2C FAQ for sequoia gpio to sdram eeprom (not local)
FreeBSD documentation on the Intel 8237 DMA controller (not local)
74HCT244 Octal buffer/driver with 3-state outputs
74HCT245 Octal bus transceiver with 3-state outputs
PCI, UMI0 and UMI1
Note where the VT82C505 datasheet and application notes differ the datasheet is incorrect
VT82C505 VL-PCI bridge
Full 505 register list
How to use 505 with non VIA core logic
For reference: VIA VT82C425 core logic, and registers
UMI0 is an ISA UMI connector.
UMI1 is a PCI UMI connector.
Super IO, kbd/mouse and parallel port
PC87307 SuperIO datasheet: PDF PS
PC87307 Example schematic: PDF or PS: 1 2 3 4 5 6 7 8 9
93C66 (rev 1) and 93C46 (id) Serial EEPROM
93C86 (rev > 1) Serial EEPROM
Notes on Parallel port and its modes (not local)
The IEEE 1284 and ECP/EPP standards (not local)
PC Keyboard FAQ
PC Mouse info (see PS/2 section)
AMI Keyboard controller manual (runs in superIO) PDF (300k) PS (18M)
Hostid flash format
Serial things: RS232, Smartcard, IR
General notes on PC Serial port and software (not local)
MAX211E RS232 driver or Analog equivalent ADM211E
74ACT05 Hex Inverter Buffer/Driver
74F153 Dual 4-Input Multiplexer
TFMS5380 Photo Module for PCM Remote Control Systems
TSIP5201 GaAs/GaAlAs IR Emitting Diodes in 5 mm Package
Smart card pinout, flex connector gets pins in order 1, 5, 2, 6, 3, 7, 4, 8.
March97 ES1887 Datasheet Part 1 and part 2
Old ES1888 Design Guide
ES888 and ES1887 differences from 1888
SSM2135 headphone amp
PC gameport/joystick interface(not local)
Crystal CS8900 Ethernet controller [Not local]
The 93C46 Serial EEPROM is not used in DNARD, it is shown for reference only
Also: (rev > 3) standard power jack (PWRJACK) Sheet 13
Bypass Caps (Sequoia)
Bypass Caps (I/O)
Bypass Caps (5)
Bypass Caps (10)
Rev 5 Wirelist, Parts, ...
- Wirelist - by part (unsorted)
- Wirelist - by signal
- BOM (SIL CAD package ascii format)
- BOM (Microsoft Excel/Office 97 format)
- BOM (web page created by excel)
- CCT Spectra router files (ZIP archive). Includes .DES design file containing netlist, component pin/pad information and placement and .w wires file containing Spectra output. Opening the .DES and doing 'read wires dnard5.w' will reconstruct the placed and routed board (note that until any routing command is issued version 7 of CCT Spectra shows up a net +UNUSED_PINS+ as unroutes). The '.do' files (used in the order: fence.do clock.do widths.do smart.do) were used to run the router. The rules report produced by the router contains a summary of the design and do file rules.
The revision 5 uses a four layer PCB. Two are signal layers, there is a ground plan (split with a single connect point for audio ground) and a power plane split into +5V, +5V(audio), and +3.3V. The following are available:
Layer 1 (component) Gerber Postscript Layer 2 (gnd) Gerber Postscript Layer 3 (power) Gerber Postscript Layer 4 (solder) Gerber Postscript
Solder Mask (top) Gerber Postscript Solder Mask (bottom) Gerber Postscript Solder Paste (top) Gerber Postscript Solder Paste (bottom) Gerber Postscript Drill Gerber Postscript Drill for NPTH Gerber Postscript
Component placement Postscript Component pin 1 indication Postscript Layout Drawing (scaled for printing) Postscript
Aperture table Text Different format text APR for GC_PREVUE Drill table Text
The pal is a MACH231-6 device from AMD. This is a 5V part, but AMD have supplied us with careful characterization of the output drivers and insein simulations suggest we can directly drive the 3.3V parts that we need to. See the notes for the cpupal sheet for more details.
The simulation source code is currently deemed to be the truth. The simulation option (built by passing this file through the C preprocessor without MACHXL defined) creates a file for our in-house simulation system, this uses the sim.h header mentioned in the code; the simulator is not available outside of DIGITAL. The MACHXL code is built as described in the comment at the start of the code. Note this code will change as we fix problems.
The pinouts come from header files for rev 1, rev 2, and rev 3, rev 4 and rev 5.
The simulation output traces show the main accesses controlled by the PAL.
The JEDEC file for the 40812 PAL includes annotations showing the MACHXL options. This PAL has been verified to work on both rev 4 and rev 5 boards.
Updated: 25th August 1997
Copyright (c) 1997 by Digital Equipment Corporation
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