General Chair

David Lepejian

General Co-Chair

Israel Koren
University of Massachusetts

Vice Chair
Yervant Zorian
Virage Logic, Inc.

Program Chair
Julie Segal

Program Co-Chair
Adit Singh
Auburn University

Program Committee

(to include)

Gerard Allan, U of Edinburgh

Benjamin Chu, IBM

Jon Colburn, HPL

Neil Harrison, Philips

Alvin Jee, HPL

Tracy Larrabee, UC Santa Cruz

Regis Leveugle, TIMA

Fabrizio Lombardi, Northeastern U

Marc Loranger, Credence

Calumn Mackay, ST

Cecilia Metra, U. of Bologna

Linda Milor, Georgia Tech

James Pak, AMD

Evanthia Papadopoulou, IBM

Nohpill Park, Oklahoma State U

Jose Pineda de Gyzez, Philips

Witold Pleskacz, Warsaw U

Manoj Sachdev, U of Waterloo

Craig Soldat, Agilent

Thomas Storey, PDF Solutions

Duncan Walker, Texas A&M U

Anthony Walton, U of Edinburgh

IEEE Computer Society

Test Technology Technical Council


Yield Optimization & Test

November 1-2, 2001, Baltimore, Maryland, USA

Held in conjunction with ITC Test Week 2001



Scope: The purpose of this workshop is to bring researchers and practitioners in the field of defect detection, defect tolerance, yield improvement , test generation and DFT. The arrival of nanometer technology has the potential of rendering today’s tools for root cause failure analysis useless. The application of extensive test data, combined with a comprehensive DFT approach and specialized tools for classification, localization and isolation presents the promise of solving this problem. This workshop should provide the ideal forum to engage discussion on this critical topic for the new millennium.

Areas of Interest include, but are not limited to

Defect identification

Fault isolation

Defect detection tools

Defect detection methodologies

Case studies of isolation

Use of failure maps in root cause analysis

DFT methods to improve isolation

Failure signatures not found in isolation

Using multiple methods to increase isolation success

Linking of design features to isolation

Use of RTL for isolation

Yield Modeling

Correlation of test data to fails

Design for Yield

Yield analysis and Yield optimization


Author information:

Authors are invited to submit email copies their full paper or an extended abstract of at least 500 words in Microsoft Word, .pdf or .ps format. Submission must include the authors’ names, presenter, address, and telephone, fax, along with whom to notify upon acceptance. Authors of accepted papers will be required to submit an illustrated text of the final paper for inclusion in the workshop digest. Proposals for panel sessions are also invited.

Author Schedule:

Deadline for Submission September 7, 2001

Notification of Acceptance September 19, 2001

Deadline for final version October 5, 2001

Authors should send papers or direct questions to:


Or Julie Segal, HPL Inc., 2033 Gateway Place, San Jose, CA 95110