Accelerated Logic started its development in
1999 with the creation of a SRAM based solid state device. This
first generation Accelerator was 128MB in size and operated in PIO
mode 1. The SRAM based Accelerator proved both our architecture
and our technical capabilities.
After the SRAM Accelerator the first SDRAM based
Accelerator was designed. This Accelerator was physically compliant
to the 5.25” form factor. Both performance and storage size increased
significantly with this design. Accelerated Logic now has the capability
to build Accelerators ranging in size from 128MB up to 4GB. IDE
data transfer performance was increased from PIO mode 1 to PIO mode
4 and even UDMA 0. In UDMA 0 the Accelerator has a sustained data
throughput of 18.1MBs.
The latest generation Accelerator is based on the
3.5” form factor and supports UDMA 33. UDMA 33 is quite a significant
milestone, since the Accelerator actually transfers data at 33MBytes
per second continually. This forms a sharp contrast to ordinary
hard disk that are only capable of bursting data at full bandwidth
for small amounts of data.
The 3.5” Accelerator is upgradeable; there is an
expansion interface available. Using this interface it is possible
to add extra storage capacity to the Accelerator. Using this architecture
it is possible to build Accelerators of 14GB in size.
Accelerated Logic is currently working at the implementation
of the UDMA 66 standard. At this stage it should be feasible to
realize UDMA 66 in the 3.5” architecture.
In parallel Accelerated Logic has formed a second
development team. This team has started the design of a Fibre Channel
interface compatible solid state storage device. Fibre Channel is
a rapidly evolving and expanding market.
For solid state storage the Fibre Channel standard
is interesting for two reasons; firstly Fibre Channel supports higher
bandwidth and therefore makes higher data transfer rates possible.
Secondly Accelerated Logic believes that Fibre Channel will become
the standard for storage area networks (SAN's).
When Accelerators can be placed in storage area
networks it makes dynamic allocation of Accelerator storage capacity