There were several reasons why this document was created. The first was simply to collect together some knowledge I have found about high-speed BDM pods for the Motorola ColdFire family of CPUs. Secondly, it will document my own design for a high-speed ColdFire BDM pod.
Motorola shipes their MCF5206eLITE evaluation boards with high-speed pod and a trial time-limited version of Mentor Graphics XRAY debugger. The pod sometimes hangs and the full version of the debugger is not very cheap. The pod is not compatible with the one from P&E (due to a minor change in several signal paths - I think it was made to make users buy their drivers). That's why I collected some knowledge about Motorola BDM and created my own pod which can be used with the free GNU Insight debugger and many others. Because I also work with Altera PLD devices, the pod can be used in two different modes - Motorola BDM and Altera ByteBlaster. In Motorola BDM mode, the pod is compatible with the commercially available BDM pod from P&E and can be used to debug ColdFire busses up to 54 MHz. In Altera ByteBlaster mode, the pod is compatible with the Altera ByteBlaster download cable and can be used with the Altera development software (MAX+PLUS II, Quartus, E+MAX) to in-system configure Altera PLD devices.
This part of the document includes the schematic diagram of the original P&E BDM pod design, and the GAL source code for the Lattice GAL16LV8C used in their design. The schematic is also available from P&E directly, it can be downloaded from their web site at: http://www.pemicro.com/products/coldfire/cablecf/cablecf.pdf. The GAL source code was obtained from Rolf Fiedler. His GAL source is known to be correct, and can be used to program a new GAL if one is accidentally destroyed. (Thanks to Rolf Fiedler for his effort here.)
P&E BDM schematic: PE_BDM_pod.gif GAL source code by Rolf Fiedler: PE_BDM_GAL.gif Another GAL source code (I don't know who is the author): icd.opl
There are apparently two changes in the P&E schematic (at least, between the schematic and the P&E pod that I saw - the pod came with older 25 MHz ColdFire evaluation board). Fist, R6 is 220 ohms, not 510 like the schematic shows. Secondly, the GAL used currently is a 15 ns device, not a 25 ns. A 25 ns GAL will barely handle a 25 MHz CPU, 15 ns GALs will not operate much above 40 MHz.
The ColdFire CPUs require that the BDM signals DSI and DSCLK are synchronized to the CPU´s clock, with certain setup and hold time requirements. A 54 MHz ColdFire CPU has 18.5 ns between clock edges, with a 4.2 ns setup time. This leaves 14.3 ns worth of time for any external device to drive these signals into the CPU. (This include the device´s internal propagation delay, plus signal propagation delays between the device and the CPU). Even with no propagation delays at all, a 15 ns device is simply too slow. A 10 ns device will probably work most of the time - but the cable between the CPU and the pod could not be longer than 15-20 cm. For longer cables a faster device is required. That was the reason why original fast pod sometimes hung. It used a 10 ns device (it means 10 ns propagation delay for output pin plus several ns for internal logic).
The input signals from the PC to the BDM pod go through signal diodes with pull-up resistors behind them (D1 through D5, and SIP1). The purpose of these components is to shift the 5V logic level from the PC´s parallel port to a 3.3V level for the GAL device. These components do not provide any significant filtering action for any electrical noise picked up by the parallel port cable, or any crosstalk created between signal lines in the cable itself.
Also, note that there is a dramatic difference between parallel port modules. Some have output filters that cause the board to generate fairly clean output signals. Other (less expensive) parallel port modules have no output filters, and create significant electrical noise and crosstalk as a result. Also, older parallel port modules had slow, open-collector outputs. The high-speed totem-pole outputs of some ECP / EPP modules create much sharper signal edges, and consequently much more noise.
The filter on the DSO signal from the CPU to the BDM pod is perhaps excessive. As the oscilloscope shows, the DSO signal from the CPU is not driven very hard at all. Consequently, the RC filter on the BDM pod doesn´t appear to be needed. The fact that P&E lowered the resistor in this filter from 510 to 220 ohms gives some indication of this, and further implies that 220 ohms may still be too much.
There are no filtering components on the outputs of the GAL that go to the CPU, or to the host PC. Series damping resistors would be helpful, on the order of 10 to 50 ohms.
One final note: There are 1 kohm termination resistors between the pod and pins 14,15,16 and 17 on the parallel port connector (signals PST0-PST3). If you check with an oscilloscope, you will discover that they are far too high in value, and that a logic "0" winds up at about 1.5V, which simply shouldn´t work at all. (Yet, the P&E pods work just fine, and so does this design. Very odd.) It appears that these lines simply are not used by any of the software debuggers. I tried to break them, the pod was working without any harm. As a result, these lines could probably be simply omitted.
The ByteBlaster download cable can be used to in-system configure Altera PLD devices. It's full datasheet can be downloaded at: http://www.altera.com/literature/ds/dsbyte.pdf. It works with all Altera design tools - MAX+PLUS II, E+MAX, QUARTUS and also with the Jam STAPL Byte-Code Player (the JBC player can be used to configure PLD devices from a jam file, without installing big development tools).
Build the pod with a solid ground plane so that filtering components will have something to "push against". Replace the GAL with a different device that is inherently more robust; that can tolerate 5V on input signal lines even with it´s local power voltages absent. (e.g. Xilinx 95xx series CPLD or Altera MAX3000A family), 7 ns device or faster. Add filters on all signal lines, both into and out of the BDM pod, to both the target ColdFire CPU and to the host PC system.
My design is based on the work of W. Mohat (firstname.lastname@example.org). He did deep analysis of the P&E pod problems, some of them are also mentioned in this text. But there were several bugs in his design (in the circuit schematic were swapped pins on the LPT port, in the Xilinx CPLD schematic were also several errors). All these problems have been fixed in my design.
The schematic of my BDM pod is very simple. Because the ColdFire eval. board uses a supply voltage of 3.3V, so does my pod design. The debugging or configuring board must put a 3.3V supply voltage to the VCC pin of the connectors V2, V3, V4 or V5. The heart of the design is a small and cheap Altera MAX3032A PLD (U1) that does all the work. It's 5V tolerant pins are pin-to-pin connected (through the filters C1-C5, C8-C9, R1-R23) to the PC LPT port connector (V1), to the Motorola BDM connector (V2) and to the Altera ByteBlaster connector (V3). There is also a universal connector (V4) that I use to configure and debug my designs (it contains all the BDM and ByteBlaster signals and is significantly smaller in size). Connector V5 can be used to in-system reconfigure the U1 chip. Because the U1 chip is a 4ns device (EPM3032ATC44-4), the ribbon cable to the ColdFire board can be longer (up to 50-70cm). A 7ns device would be fast enough for most applications. You can use EPM3032ATC44-7 instead of EPM3032ATC44-4 without any changes in the design.
Switch SP1 determines the interface mode: pins 2-4 connected - Altera ByteBlaster mode pins 2-4 disconnected - Motorola BDM mode There are two options for the ByteBlaster mode: pins 1-2 connected - add ColdFire to the JTAG-chain pins 1-2 disconnected - JTAG-chain without ColdFire
Adding ColdFire to the JTAG-chain is useful during board diagnostics. Because MCF5206e uses for signals TDI/DSI, TDO/DSO and TMS/BKPT the same pins, the pod uses them either as BDM or JTAG signals. To enable ColdFire JTAG mode, ColdFire's pin TCK (122) must be connected to the JTCLK pin of the V4 connector and JTAG pin (129) must be connected to the JTCF pin of the V4 connector.
ColdFire debugging - SP1 pins 2-4 disconnected (Motorola BDM mode) - SP1 pins 1-2 disconnected - ColdFire connected to the V2 or V4 connector ByteBlaster JTAG / ByteBlaster PS PLD configuration - SP1 pins 2-4 connected (Altera ByteBlaster mode) - SP1 pins 1-2 disconnected - configured device connected to the V3 or V4 connector JTAG with ColdFire - SP1 pins 2-4 connected (Altera ByteBlaster mode) - SP1 pins 1-2 connected (JTAG-chain with ColdFire) - ColdFire and devices in a JTAG-chain connected to the V4 connector JTAG without ColdFire - SP1 pins 2-4 connected (Altera ByteBlaster mode) - SP1 pins 1-2 disconnected (JTAG-chain without ColdFire)
- devices in a JTAG-chain connected to the V3 or V4 connector
Here is the schematic of my BDM pod design: BDM_JTAG_interface.gif And the logical schematic of the used PLD: Altera MAX.gif
Complete design files are also available in a source format:
OrCAD Capture 9.2 schematic:C:\Dokumenty\Různé\Web\BDM\BDM_JTAG_interface.dsn.zip Altera MAX+PLUS II v10 design files including compiled jam, jam byte code and programmer object files: Altera_MAX.zip
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