The 8086 / 80286 / 80386 / 80486 Instruction Set

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The Instructions

Intel 8086 Family Architecture

General Purpose Registers
AH/AL AX (EAX) Accumulator
CH/CL CX (ECX) Counter

(Exx) indicates 386+ 32 bit register

Segment Registers
CS Code Segment
SS Stack Segment
DS Data Segment
ES Extra Segment
(FS) 386 and newer
(GS) 386 and newer

Pointer Registers Stack Registers
SI (ESI) Source Index SP (ESP) Stack Pointer
DI (EDI) Destination Index BP (EBP) Base Pointer
IP Instruction Pointer

Status Registers
FLAGS Status Flags

Special Registers (386+ only)
CR0 Control Register 0 DR0 Debug Register 0
CR2 Control Register 2 DR1 Debug Register 1
CR3 Control Register 3 DR2 Debug Register 2
DR3 Debug Register 3
TR4 Test Register 4 DR6 Debug Register 6
TR5 Test Register 5 DR7 Debug Register 7
TR6 Test Register 6
TR7 Test Register 7

Default Segment Valid Overrides
DI strings ES None
SI strings DS ES, SS, CS

Instruction Clock Cycle Calculation

Some instructions require additional clock cycles due to a "Next Instruction Component" identified by a "+m" in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating "m":

not applicable
"m" is the number of bytes in the next instruction
"m" is the number of components in the next instruction (the instruction coding (each byte), plus the data and the displacement are all considered components)

8088/8086 Effective Address (EA) Calculation

Description Clock Cycles
Displacement 6
Base or Index (BX,BP,SI,DI) 5
Displacement+(Base or Index) 9
Base+Index (BP+DI,BX+SI) 7
Base+Index (BP+SI,BX+DI) 8
Base+Index+Displacement (BP+DI,BX+SI) 11
Base+Index+Displacement (BP+SI+disp,BX+DI+disp) 12
  1. add 4 cycles for word operands at odd addresses
  2. add 2 cycles for segment override
  3. 80188/80186 timings differ from those of the 8088/8086/80286

Task State Calculation

"TS" is defined as switching from VM/486 or 80286 TSS to one of the following:

New Task
Old Task486 TSS (VM=0)486 TSS (VM=1) 386 TSS (VM=0)386 TSS (VM=1)286 TSS
386 TSS (VM=0) 309 226 282
386 TSS (VM=1) 314 231 287
386 CPU/286 TSS 307 224 280
486 CPU/286 TSS 199 177 180


  • All timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing.
  • To convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: (1000MHz/(n MHz)) = X nanoseconds

    FLAGS - Intel 8086 Family Flags Register

    Bit # (in hex)Acronym Description
    0 CF Carry flag
    1 1
    2 PFParity
    3 0
    4AFAuxiliary flag
    6ZFZero flag
    7SFSign flag
    8TPTrap flag (single step)
    9IFInterrupt flag
    ADFDirection flag
    BOFOverflow flag
    C,DIOPLIOPL I/O Privilege Level (286+ only)
    E NT Nested Task Flag (286+ only)
    F 0
    10 RF Resume Flag (386+ only)
    11 VM Virtual Mode Flag (386+ only)
    12 AC Alignment Check (486SX+ only)
    13VIFVirtual Interrupt Flag (Pentium+)
    14VIPVirtual Interrupt Pending (Pentium+)
    15ID Indentification (Pentium+)

    MSW - Machine Status Word (286+ only)

    Bit # AcronymDescription
    0 PE Protection Enable, switches processor between protected and real mode
    1 MP Math Present, controls function of the WAIT instruction
    2 EM Emulation, indicates whether coprocessor functions are to be emulated
    3 TS Task Switched, set and interrogated by coprocessor on task switches and when interpretting coprocessor instructions
    4 ET Extension Type, indicates type of coprocessor in system
    5-30 Reserved
    31 PG Paging, indicates whether the processor uses page tables to translate linear addresses to physical addresses

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