STEbus pinout

Pin Function Row Function
a c
1 GND o o GND
2 +5V o o +5V
3 D0 o o D1
4 D2 o o D3
5 D4 o o D5
6 D6 o o D7
7 A0 o o GND
8 A2 o o A1
9 A4 o o A3
10 A6 o o A5
11 A8 o o A7
12 A10 o o A9
13 A12 o o A11
14 A14 o o A13
15 A16 o o A15
16 A18 o o A17
17 CM0 o o A19
18 CM2 o o CM1
19 ADRSTB* o o GND
20 DATACK* o o DATSTB*
21 TRFERR* o o GND
22 ATNRQ0* o o SYSRST*
23 ATNRQ2* o o ATNRQ1*
24 ATNRQ4* o o ATNRQ3*
25 ATNRQ6* o o ATNRQ5*
26 GND o o ATNRQ7*
27 BUSRQ0* o o BUSRQ1*
28 BUSAK0* o o BUSAK1*
29 SYSCLK o o VSTBY
30 -12V o o +12V
31 +5V o o +5V
32 GND o o GND
Connector: DIN41612. Seen: Looking into backplane.

* indicates active low signal

GND: Ground reference voltage

+5V: Powers most logic.

+12V: -12V: Primarily useful for RS232 buffer power.

+12V and -12V have other uses apart from RS232 power. The +12V has been used for programming voltage generators. Both can be used in analogue circuitry, but note that these are primarily power rails for digital circuitry and as such they often have digital noise. Some decoupling or local regulation is recommended for analogue circuitry.

VSTBY: Standby voltage. Optional. This line is reserved for carrying a battery backup voltage to boards that supply or consume it. A 3.6V NiCad battery is a common source. The STEbus spec is not rigid about where this should be sourced from.

In practice, this means that most boards requiring backup power tend to play safe and have a battery on board, often with a link to allow it to supply or accept power from VSTBY. Hence you can end up with more batteries in your system than you need, and you must then take care that no more than one battery is driving VSTBY.

D0...7: Data bus. This is only 8-bits wide, but most I/O or memory-mapped peripherals are byte-oriented.

A0...19: Address bus. This allows up to 1 MByte of memory to be addressed. Current technology is such that processor requiring large amounts of memory have this on the processor board., so this is not a great limitation.

CM0...2: Command Modifiers. These indicate the nature of the data transfer cycle.

ATNRQ0...7: Attention Requests. These are reserved for boards to signal for processor attention, a term which covers Interrupts and Direct Memory Access (DMA). The wise choice of signal does not commit these lines to being specific types, such as maskable interrupts, non-maskable interrupts, or DMA.

The number of Attention Requests reflects the intended role of the STEbus, in real-time control systems. Eight lines can be priority encoded into three bits, and is a reasonably practical number of lines to handle.

BUSRQ0...1 and BUSAK0...1: Bus Requests and Bus Acknowledge. Optional. Used by multi-master systems.

The number of Attention Requests reflects that the STEbus aims to be simple. Single-master systems are the norm, but these signals allow systems to have secondary bus masters if needed.

DATSTB*: Data Strobe. This is the primary signal in data transfer cycles.

DATACK*: Data Acknowledge. A slave will assert this signal when to acknowledge the safe completion of a data transfer via the STEbus.

TRFERR*: Transfer Error. A slave will assert this signal when acknowledging the erroneous completion of a data transfer via the STEbus.

ADRSTB*: Address Strobe. This signal indicates the address bus is valid. A long time ago, this had some practical use in DRAM boards which could start strobing the address lines into DRAM chips before the data bus was ready. The STEbus spec was later firmed up to say that slaves were not allowed to start transfers until DATSTB* was ready, so ADRSTB* has become quite redundant. Nowadays, STEbus masters simply have to generate DATSTB*. ADRSTB* is often created from the same signal as DATSTB*. Slaves simply note when DATSTB* is valid (since the bus definition insists that the address will also be valid at the same time as the data.

SYSCLK: System Clock. Fixed at 16MHz. 50% duty cycle.

SYSRST*: System Reset.