VhdlCohen Publishing
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Main Training VHDL Models (Code) Links Return Policy

http://WWW.EMACS.ORG/hdl
http://www.EMACS.ORG/
VHDL, VERA,  CSH MODE, & VERILOG MODE 
http://www.OpenMore.com Excel Spreadsheet for code assessment
http://www.opencores.org/OIPC/projects/OpenTech
Comp.Lang.Vhdl Newsgroup
http://www.angelfire.com/in/rajesh52/verilog.html
http://www.egroups.com/group/ASICDESIGN
http://www.fpga-guru.com/
http://members.nbci.com/_XMCM/vhdlweb/index.html
http://tech-www.informatik.uni-hamburg.de/vhdl/
http://www.enetis.net/~mitch/hdlsources.html
http://www.estec.esa.int/microelectronics/core
Open Hardware designs and free tools distribution cdrom
Vhdl Newsgroup via http://www.deja.com
Rajesh Bawankule Center -- Vlog FAQ, Tips, books, tools, jobs
Discussion group on ASIC and FPGA designs, founded Oct 2000
Andraka Consulting Group, Inc -- Useful links, models, info
VHDL Web -- Sites with many links
University of Hamburg -- great site with lots of links
Internet Sources of HDL Models and links
Several cores, including PCI 
http://www.vsi.org
http://www.vhdl.org/siwg
http://janick.bergeron.com/guild
http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=SRSSTANDARDS
http://www.model.com
http://www.cadence.com/
http://www.synplicity.com
http://www.altera.com
http://www.novas.com
http://www.synopsys.com
http://www.chronology.com/
http://www.cleveldesign.com/
http://www.nuthena.com/
http://www.testbuilder.net
http://www.Transeda.com/
http://www.verisity.com/ 
http://www.yxi.com
Virtual Socket Interface Alliance TM
VHDL Synthesis Interoperability Working Group
Verification Guild
Motorola's  Semiconductor Reuse Standards
Model Technology 
Cadence 
Synplicity 
Altera 
Novas -- debug solutions for Verilog and VHDL
Synopsys
Chronology
C level design -- from C/C++ code to HDL code 
Foresight, HW/SW Co-Design, Simulation and Coverification.
Cadence Testbuilder, verification with C++ TB class library
Transeda  -- Design Verification, Parametric Design Rule Checker
Verisity  -- Functional verification automation, coverage, linting
YXI -- Design Reuse, Design Exploration and Design Synthesis 
http://klabs.org/richcontent/MAPLDCon02/MAPLDCon02.html 
2002 MAPLD International Conference September 10-12, 2002

http://klabs.org/richcontent/MAPLDCon03/MAPLDCon03.html
2003 MAPLD International Conference
Reagan International Trade Center
Washington, D.C. September 9-11, 2003
 

http://klabs.org/richcontent/MAPLDCon02/ProgramSessions/Session_P.html 
Paper P30  Coding HDL for Reviewability  Ben Cohen
Presentation: p30_cohen_s.ppt p30_cohen_s_appendix.ppt
 

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P.O. Box 2362, Palos Verdes Peninsula CA 90274-2362