Chip-select Unit: The Chip-select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-selects. The individual chip- selects become valid in the same bus state as the address and become inactive when either a new address is selected or the current bus cycle is complete. The CSU is divided into eight separate chip-select regions, each of which can enable one of the eight chip-select pins. Each chip-select region can be mapped into memory or I/O space. A memory chip-select region can start on any 2(n+1) Kbyte address location (where n = 0 - 15, depending upon the mask register). An I/O-mapped chip-select region can start on any 2(n+1) byte address location (Where n = 0 - 15, depending upon the mask register). The size of the region is also dependent upon the mask used.
DMA and Bus Arbiter Unit: The Intel 386EX microprocessor's DMA controller is a two-channel DMA; each channel operates independently of the other. Within the operation of the individual channels, several different data transfer modes are available. These modes can be combined in various configurations to provide a very versatile DMA controller. Its feature set has enhancements beyond the 8237 DMA family; however, it can be configured such it can be used in an 8237-like mode. Each channel can transfer data between any combination of memory and I/O with any combination (8 or 16 bits) of data path widths. An internal temporary register that can disassemble or assemble data to or from either an aligned or unaligned destination or source optimizes bus bandwidth.
The bus arbiter, a part of the DMA controller, works much like the priority resolving circuitry of a DMA. It receives service requests from the two DMA channels, the external bus master, and the DRAM Refresh controller. The bus arbiter requests bus ownership from the core and resolves piority issues among all active requests when bus mastership is granted.
Each DMA channel consists of three major components: the Requestor, the Target, and the Byte Count. These components are identified by the contents of programmable registers that define the memory or I/O device being serviced by the DMA. The Requestor is the device that requires and requests service from the DMA controller. Only the Requestor is considered capable of initializing or terminating a DMA process. The Target is the device with which the Requestor wishes to communicate. The DMA process considers the Target a slave that is incapable of controlling the process. The Byte Count dictates the amount of data that must be transferred.
Timer Control Unit: The Timer Control Unit (TCU) on the Intel 386EX microprocessor has the same basic functionality as the industry-standard 82C54 counter/timer. The TCU provides three independant 16-bit counters, each capable of handling clock inputs up to 8 MHz. This maximum frequency must be considered when programming the input clocks for the counters. Six programmable timer modes allow the counters to be used as event counters, elapsed-time indicators, programmable one-shots, and in many other applications. All modes are software programmable.
Interrupt Control Unit: The Intel 386EX microprocessor's Interrupt Control Unit (ICU) contains two 8259A modules connected in a cascade mode. The 8259A modules make up the heart of the ICU. These modes are similar to the industry standard 8259A architecture.
The Interrupt Control Unit directly supports up to eight external (INT7:0) and up to eight internal interrupt request signals. Pending interrupt requests are posted in the Interrupt Request Register, which contains one bit for each interrupt request signal. When an interrupt request is asserted, the corresponding Interrupt Request Register bit is set. The 8259A module can be programmed to recognize either an active-high level or a positive transition on the interrupt request lines. An internal Priority Resolver decides which pending interrupt request (if more than one exists) is the highest priority, based on the programmed operating mode. The Priority Resolver controls the single interrupt request line to the CPU. The Priority Resolver's default priority scheme places the master interrupt controller's IR0 as the highest priority and the master's IR7 as the lowest. The priority can be modified through software.
Besides the eight interrupt request inputs available to the Intel 386EX microprocessor, additional interrupts can be supported by cascaded external 8259A modules. Up to four external 8259A units can be cascaded to the master through connections to the INT3:0 pins. In this configuration, the interrupt acknowledge (INTA#) signal can be decoded externally using the ADS#, D/C#, W/R#, and M/IO# signals.
Asynchronous Serial I/O Unit: The Intel 386EX microprocessor's asynchronous Serial I/O (SIO) unit is a Universal Asynchronous Receiver/Transmitter (UART). Functionally, it is eqivalent to the National Semiconductor NS16450 and INS8250. The Intel 386EX microprocessor contains two full-duplex, asynchronous serial channels.
The SIO unit converts serial data characters received from a peripheral device or modem to parallel data and converts parallel data characters received from the CPU to serial data. The CPU can read the status of the serial port at any time during its operation. The status information includes the type and the condition of the transfer operations being performed and any errors (parity, framing, overrun, or break interrupt).
Each asynchronous serial channel includes full modem control support (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#) and is completely programmable. The programmable options include character length (5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity (even, odd, forced, or none). In addition, it contains a programmable baud-rate generator capable of clock rates from 0 to 512 Kbaud.
Synchronous Serial I/O Unit: The Synchronous Serial I/O (SSIO) unit provides for simultaneous, bidirectional communications. It consists of a transmit channel, a receive channel and a dedicated baud-rate generator. The transmit and receive channels can be operated independantly (with different clocks) to provide non-lockstep, full-duplex communications; either channel can originate the clocking signal (Master Mode) or receive an externally generated clocking signal (Slave Mode).
The SSIO provides numeous features for ease and flexibility of operation. With a maximum clock input of 12.5 MHz to the baud-rate generator, the SSIO can deliver a baud rate of 5 Mbits per second. Each channel is double buffered. The two channels share the baud-rate generator and a multiply- by- two transmit and receive clock. The SSIO supports 16-bit serial communications with independantly enabled transmit and receive functions and gated interrupt outputs to the interrupt controller.
DRAM/PSRAM Refresh: The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated address and clock counters. Integrating the RCU into the processor allows an external DRAM controller to use chip- selects, wait state logic, and status lines.
The Intel 386EX microprocessor's RCU consists of four basic functions. First, it provides a programmable- interval timer that keeps strack of time. Second, it provides the bus arbitration to gain control of the bus to run refresh cycles. Third, it contains the logic to generate row addresses to refresh DRAM rows individually. And fourth, it contains the logic to signal the start of a refresh cycle.
Additionally, it contains a 13-bit address counter that forms th refresh address, supporting DRAMs with up to 13 rows of memory cells (13 refresh address bits). This includes all practical DRAM sizes for the Intel 386EX microprocessor's 64 Mbyte address space.
Watchdog Timer Unit: The Watchdog Timer (WDT) unit consists of a 32-bit down- counter that decrements every PH1P cycle, allowing up to 4.3 billion count intervals. The WDTOUT pin is driven high for sixteen CLK2 cycles when the down- counter reaches zero (the WDT times out). The WDTOUT signal can be used to reset the chip, to request an interrupt, or to indicate to the user that a ready- hang situation has ocurred. The down- counter can also be updated with a user- defined 32-bit reload value under certain conditions. Alternatively, the WDT unit an be used as a bus monitor or as a general- purpose timer.
JTAG Test-logic Unit: The JTAG Test-logic Unit provides access to the device pins and to a number of other testable areas on the device. It is fully compliant with the IEEE 1149.1 standard and thus interfaces with five dedicated pins: TRST#, TCK, TMS, TDI, and TDO. It contains the Test Access Port (TAP) finite- state machine, a 4- bit instruction register, a 32- bit identification register, and a single- bit bypass register. The Test-logic unit also contains the necessary logic to generate clock and control signals for the Boundary Scan chain.
Since the test- logic unit has its own clock and reset signals, it can operate autonomously. Thus, while the rest of the microprocessor is in Reset or Power- down, The JTAG unit can read or write various register chains.
Parallel I/O Unit: The Intel 386EX microprocessor has three 8-bit, general purpose I/O ports. All port pins are bidirectional, with CMOS- level input and outputs. All pins have both a standard operating mode and a peripheral mode (a multiplexed function), and all have similar sets of control registers located in I/O address space. Port 1 and 2 provide 8mA of drive capability, while port 3 provides 16 mA.
Clock Generation and Power Management Unit: The clock generation circuit includes a divide- by- two counter, a programmable divider for generating a prescaled clock (PSCLK), a divide- by- two counter for generating baud- rate clock inputs, and Reset circuitry. The CLK2 input provides the fundamental timing for the chip. It is divided by two internally to generate a 50% duty circle Phase 1 (PH1) and Phase 2 (PH2) for the core and integrated peripherals. For power management, separate clocks are routed to the core (PH1C/PH2C) and the peripheral modules (PH1P/PH2P).
Two Power Management modes are provided for flexible power- saving options. During Idle mode, the clocks to the CPU core are frozen in a known state (PH1C low and PH2C high), while the clocks to the peripherals continue to toggle. In Powerdown mode, the clocks to both core and peripherals are frozen in a known state (PH1C low and PH2C high). The Bus Interface Unit will not honor any DMA, DRAM refresh, or HOLD requests in Powerdown mode because the clocks to the entire device are frozen.
Static i386SX Core: The Intel 386EX microprocessor uses the same 32- bit core as that of the standard Intel 386SX microprocessor, with some enhancements to make it suitable for the needs of the embedded market.
The Intel 386EX microprocessor core is fully static, which means that the processor will remain its state even when the incoming clock signal is removed. The Intel 386EX can operate with 3.0V at 16 MHz, 3.3V at 20 MHz, and 5.0V at 25 MHz.