28.08.2008 12:14

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Fujitsu shows off SPARC64 VII

Fujitsu has presented technical details of the SPARC64 VII server processor at the Hot Chips Conference. As was promised two years ago, the seventh generation of the chip is compatible with its predecessors. It has four cores, each of which can execute two threads in parallel (simultaneous multithreading, SMT), and has 6 MB of L2 cache. The chip measures 20 mm × 20 mm and consists of 600 million transistors.

The individual cores are essentially the same as those of its predecessor, SPARC64 VI. Newly added are hardware barriers, that coordinate the cores with each other. They can now handle simultaneous multithreading, not just vertical multithreading like their predecessors. A few registers have been doubled to achieve this but, as before, some stages in the sixteen-stage pipeline – Fetch, Issue and Commit – have to share the two threads. There are a few new instructions as well, including one for explicit prefetches.

Fujitsu has improved the Reliability, Availability and Serviceability (RAS) functions a little: ECC bits now also safeguard all the integer registers, and the number of checkers has risen to around 3400.

At the close of the presentation, some brief details of key data for the next SPARC64 generation, codenamed Venus, was shown: SPARC64 VIII will have eight cores, be manufactured in a 45 nm process, and run at 128 GFLOPS per socket. (anw/c't)

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