The Intel i860 (N10) microprocessor delivers supercomputer performance in a single VLSI component. The 64-bit design of the i860 balances integer, floating point, and graphic performance. The Intel i860 has features of both a digital signal processor and a data processor. However, because of its speed in doing typical DSP operations, it has been extensively used in the DSP role. Its architecture also makes it suitable for other applications including engineering workstations, scientific computing, 3-D graphics workstations, and multi-user systems. The i860 is used as the data processor in Intel's massively-parallel Touchstone and Paragon supercomputers.
FeaturesParallel architecture that supports up to three operations per clock
High performance design
- One integer or control instruction per clock
- Up to two floating-point results per clock
High level of integration on one chip
- 33.3/40 MHz clock rates
- 64-bit external data bus
- 64-bit internal instruction cache bus
- 128-bit internal data cache bus
Compatible with industry standards
- 32-bit integer and control unit
- 32/64-bit pipelined floating point adder and multiplier units
- 64-bit 3-D graphic unit
- Paging unit with translation lookaside buffer
- 32x32-bit integer register file
- 16x64-bit FPU register file
- 4 Kbyte instruction cache
- 8 Kbyte data cache
Easy to use
- ANSI/IEEE Standard 754-1985 for binary floating-point arithmetic
- Intel 386/i486 microprocessor data formats and page table entries
- JEDEC 168-pin ceramic Pin Grid Array package
- On-chip debug register
- Assembler, Linker, Simulator, Debugger, C and FORTRAN Compilers, FORTRAN Vectorizer, Scalar and Vector Math Libraries for both OS/2 and UNIX environments
- 80 peak single precision MFLOPS (40MHz i860)
- 60 peak double precision MFLOPS (40MHz i860)
- 80 peak double precision MFLOPS (40MHz i860XR)
- 42 SPECmark (40MHz i860XR)
The i860XP (N11) is an extension to i860, with MP support (enable physical snooping), new process, and better performance. The i860XP microprocessor is designed around a RISC core and incorporates three additional functional units (multiply, add, and graphics) within a pipelined floating point unit. Available in 40 MHz and 50 MHz versions. The four-way set associative 16-KByte instruction and 16-KByte data caches use a MESI (modified, exclusive, shared, or invalid) cache coherency protocol. The i860XP can also support a secondary cache.
The i860 microprocessor consists of 9 units:
- Core Execution Unit
- Floating-Point Control Unit
- Floating-Point Adder Unit
- Floating-Point Multiplier Unit
- Graphics Unit
- Paging Unit
- Instruction Cache
- Data Cache
- Bus and Cache Control Unit
The core execution unit controls overall operation of the i860 microprocessor. A set of 32 x 32-bit general-purpose registers are provided for the manipulation of integer data.
The floating-point hardware is connected to a separate set of floating-point registers, which can be accessed as 16 x 64-bit registers, or 32 x 32-bit registers.
The floating-point control unit controls both the floating-point adder and the ploating-point multiplier, issuing instructions, handling all source and result exeptions, and updating status bits in the floating-point status register.
The floating-point adder peforms addition, substraction, comparation, and conversions on 64- and 32-bit floating-point values.
The floating-point multiplier peforms floating-point and integer multiply and floating-point reciprocal operations on 64- and 32-bit floating-point values.