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This is the semipublic wiki at comp-arch.net.

Since there is currently nothing on the website other than this wiki, you may have been redirected here from http://semipublic.comp-arch.net, or from the overall http://comp-arch.net.

See comp-arch.net Overview and Administrivia for an overview of why this site exists.

See Topics for CompArch wiki for something like a technical table of contents. Although be warned that many topic pages may not be linked into this hierarchical structure - they may be linked to only from

Including Topics for CompArch wiki here, since that is what most people want to go to:

There are currently 289 articles in this wiki. (Some may be support, infrastructure, or administrivia.)

Contents

What should be on this wiki

Topics for CompArch wiki

This is not expected to be a full or final list. Rather, it is hoped to be just a start - topics that I want to write essays on.

See What Kind of Topics for CompArch Wiki?

See Bad, Good, and Middling Ideas in Computer Architecture

See Ideas As To Where To Get CompArch Wiki Topics


See Wanted Pages, with discussion


WikiWish: I wish that this was a clickable, folding/unfolding, list. (TBD: choose one of the many, many, examples of such code.) Currently this is an odd mix of sections and lists. I really want it to be a TopicTree.

Categories for CompArch wiki

In addition to the topics, listed in something like a Table of contents (TOC) below, I will also try to take advantage of mediawiki's [1] to organize the pages.

The mediawiki categories are NOT a substitute for a Table of contents (TOC) or TopicTree. They are just convenient, an add-on, more easily maintained in some ways. They are not a complete tree: they are only provided for topics that experience has shown have many subtopic pages.

The categories are arranged'

Often enough new categories not above may be created - see Special:Categories.

Topic Related Categories


Parallel programming and synchronization often includes aspects of both ISA and uarch:

Corresponding topic pages

Parallel programming and synchronization often includes aspects of both ISA and uarch:


Incoming Topics

Topics that I have not yet organized into the tree. Typically these are topics that I have sketched out in my head, possibly even completely written, but which I have not yet had the time to enter in yet.

See TBD.

See also Vocabulary to-do list.

The Vocabulary to-do list is more a list of items. Whereas this Incoming Topics list is usually a list of mini-essays or discussions


  • Unusual Operations
delt - Sun SX pixel processor. (1995). "Add four delta values cumulatively giving 4n-long vector."
I think this amounts to r0=s0+d0, r1=s1+d0+d1, r2=s2+d0+d1+d2, r3=s3+d0+d1+d2+d3
I.e. sum prefix of the delta vector, and a vector-vector add, i.e. vadd(s+sumprefix(d))
Q what is it used for?
Or, sumprefix(s+d)
plot - "Bresenham interpolation to vector"
  • Intel genX plane, line, blend


What is Computer Architecture?

See Computer Architecture: Different Levels of Abstraction

Instruction Set Architecture

Register Architecture

Basic Instruction Concepts

Basic Flow Control Instructions

Funky control-flow stuff:

Basic Data Types

  • Addresses / Pointers
  • Offsets

Less common

  • strings - usually strings are arrays of small byte-sized integers, counted or terminated. Possibly lists.
  • FP16
  • FP80, FP128
  • Complex Numbers - usually FP, sometimes integers

Basic Integer Instructions

Basic Floating Point Instructions

Basic System ISA

Basic Memory Reference Instructions

SIMD and vector ISAs

Special Instructions

  • ABS absolute value, and related instructions such as SAD, sum of absolute difference

String and Block Memory Operations

Extending an ISA

Extending an instruction set architecture is one of the fundamental tests of an ISA.

  1. Increasing Register Width: Overlaid vs. Extended
  2. Increasing Register Count

See API or instruction to decode an instruction

Instruction Set Groups

Commonly Seen:

Less Common:

Cross Cutting:

Instruction Set Extensions, a Rough History

This section presents recent significant instruction set extensions in an approximately historical order and context for major current companies.

TBD: extend far enough back into the past to see the wheel of reincarnation.

TBD: make predictions about instruction set futures.

Instruction Formats

Predicates

  • Predicate field in instruction

Data Types

Less standard:

Microarchitecture

Modern Microarchitecture Examples

Let us walk through a modern microarchitecture. This provides us a place to hang certain topics.

or M - Map
or ROB - ReOrder Buffer

Hanging Topics Off the Pipeline

Now that we have generic names for such pipestages, we can hang some topics, ranging from simple to advanced, off them.

TBD: many, many, topics need to be hung up above.

TBD: what I really need is one such tree object for the pipeline, with multiple views - one view with little detail, one view with more. I like such "show the overview", "show the detail", "now zoom in". Automatically maintained to prevent inconsistencies. Unfortunately, this is yet another WikiWish, something I hope to add to this wiki in my copious spare time. Might be able to approximate by using one of Mediawiki's automatically generated TOCs.


BP - Branch Prediction

Branch Predictor Subcomponents

Branch prediction history

IF - Instruction Fetch

Trace BTB

ID - Instruction Decode


RR - Register Rename or M - Map

RD - Register Read

S - Schedule


EX - Execute

MEM - Memory Access, usually Data Cache Access

It is surprisingly challenging to maintain the ability to retire (commit) 1 store per cycle - let alone more. You cannot fall into the trap of initiating the store at retirement, and then waiting until it is a confirmed hit (in a writeback cache - let alone in store-through) before initiating the next.

Instruction Window

Pipelining

Parallelism


Predictors and Caches

Two standard techniques in computer architecture are predictors and caches. By this point in time these can be considered well known and obvious.

See the topic page for a design tree by me, preserved by Mark Smotherman.

See also Taxonomy of Patterns for Prefetchers

Varieties of Cache

VLSI Layout Issues

Arrays

One of the most common hardware data structure classes is the array. Specifically, array of memory elements, although arrays of logic and arrays of processing elements are also of interest.



I'm not sure that I like the term "RAM", Random Access Memory. Something like Fixed Address Memory might be more descriptive, since over the years such memories have become less and less randomly accessible


There are two forks in the discussion of CAM arrays.
  1. True CAMs - all of the flavors of CAMs
  2. The more basic question of how to implement a simple non-priority CAM - aka a cache with tags and data

Schedulers

One of the most common hardware functions is scheduling, picking, or prioritization. Not just in OOO schedulers. The scoreboards of in-order processors are really schedulers. But also in memory schedulers, selecting what memory access to handle next, etc.

Caches

Varieties of Cache

Cache Terminology

Memory Ordering

  1. Strong Ordering or Sequential Consistency
  2. Weak Consistency
    1. Eventual Consistency
  3. Intermediate Consistency
    1. Processor Consistency
    2. TSO
    3. Causal Consistency
  1. Message Passing Ordering
  1. Fence Instructions

Memory Optimizations

See also Memory coalescing

Synchronization

-

-

-

-

-

Interconnect

  1. Busses
  2. Interconnection Networks
    1. Rings
    2. Meshes
    3. Hierarchies
      1. Fat Trees, etc.

Virtual Memory

High Speed Design

Memory

Memory Alignment

Operating System and Other Privilege Architecture

Virtual Machines

Security

Stack Protection
Since stack clobbering, buffer overflows on mixed data/return address stacks, is a common source of security problems, there have been many band-aid proposals that fix just this aspect of computer (in)security, including:

as well as some that particularly help this, although are of more general use

Coprocessors

Performance Measurement and Debugging Features

TBD


Reliability, Availability, and Serviceability (RAS)

Power and Energy

Integration

Advanced Topics

"Conventional" Alternative or Advanced Computer Architecture

See Andy Glew's Pet Topics in Computer Architecture for stuff that is especially interesting to me. Also BS: Bluesky, Brainstorming, Bullshit

Topics listed here are "conventional", in that many people have proposed them, often time and again.

The following are similarly often proposed topics, but these are topics I am more sympathetic to.

Less often proposed

Why I am more sympathetic to complex arithmetic than I am to interval arithmetic

Andy Glew's Pet Topics in Computer Architecture

Hey, this is my wiki - why can't I indulge my pet topics?

.


BS: Bluesky, Brainstorming, Bullshit

The boundary between an advanced topic and BS is variable.

Tools in the Toolkit

Hardware data structures



Tricks and hacks:

Topics for the Professional Computer Architect - and Wannabe

Many more people are wannabe computer architects than get paid to it. Heck: I was a wannabe before it became my job, and I still am!

Many people have job descriptions that say computer architect, but are not.

Reading List for Computer Architecture

I am often asked for a recommended reading list. Might as well record it.

Terminology, Vocabulary, and Taxonomy





Copyrights and Other Intellectual Property Rights

See CompArch:Copyrights and Other Intellectual Property Rights.

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