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Is 3D IC Packaging Ready For Prime Time?

As materials, architectures, thermal management, software, standards, and process improvements move forward, the semiconductor IC industry edges closer to true 3D ICs.

Roger Allan

December 28, 2011

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After several years of trying to perfect the technology of 3D IC packaging, the stage is now set for fruitful results. In fact, several IC industry experts predict that this will be the year 3D ICs make their commercial debut. Refinements in through-silicon via (TSV) interconnect technology will be key enablers.

Some 2.5D chips have been commercially available, and field-programmable gate arrays (FPGAs) are making a competitive push to 3D architectures. But most semiconductor IC experts believe that making devices and packaging them using 3D ICs with TSV technology is the ultimate goal and the “state of the art.”

This is supported by developments coming out of semiconductor companies like Samsung, Intel, ST-Ericsson (a joint venture between STMicroelectronics and Ericsson), and IBM. Another indicator is that the pace of 3D IC activity among companies, research centers, universities, and standards organizations has been frenetic (see “A Host Of 3D IC Collaborations And Standardization Efforts Emerging” at electronicdesign.com).

IBM has been mass-producing full-fledged 3D ICs for high-volume mobile consumer electronics devices using low-density TSVs. But the company has kept this work under wraps until recently when it announced 3D IC technology at last month’s IEEE International Electron Devices Meeting (IEDM). Micron Technology Inc. will use IBM’s advanced TSV technology in its Hybrid Memory Cube (HMC), which is expected to achieve speeds 15 times faster than today’s technology in a 90% smaller package (Fig. 1). The device will be manufactured at IBM’s fabrication facility in East Fishkill, N.Y., using IBM’s 32-nm high-K metal-gate process.

IBM’s approach so far has been to use low-density TSVs. The company has identified one major hurdle, the need for solving the overheating problem in 3D ICs with TSVs. To solve this, IBM is working closely with 3M, which is looking at making a “designer” material that fits between stacked dice and is an electrical insulator, but is also more thermally conductive than silicon.

According to IBM, HMC combines high-performance logic with Micron’s state-of-the-art DRAM technology. Prototypes will feature bandwidths of 128 Gbytes/s, while state-of-the-art capabilities offer 12.5 Gbytes/s. It also requires 70% less energy to transfer data in a much smaller form factor.

The HMC 3D technology, IBM says, will enable a new generation of performance in applications ranging from large-scale networking and high-performance computing to industrial automation and eventually computer products.

“This is a milestone in the industry’s move to 3D semiconductor manufacturing,” says Subu Iyer, IBM Fellow.

“It is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiency,” agrees Robert Feurle, vice president of DRAM marketing for Micron.

Just when such a product will become available is not clear, but most experts believe it may become available sometime this year or next. They also caution that many other issues need a solution, not just thermal management. Even IBM agrees with that assessment.

“You’re not going to win the 3D IC performance battle if you rely solely on materials, or on chip architecture, or networking, or software and integration. You must use all these resources together at the most holistic level,” explains Bernard Meyerson, vice president of research at IBM’s facility in Armonk, N.Y.

Robert Patti, chief technology officer and VP of design engineering at Tezzaron Semiconductor, concurs with this view. He points out that using normal 2D tool flow software—even refined versions for 3D ICs with TSVs—is not enough.

Tezzaron points to a prototype IC it is building with several partners that is the result of using advanced 3D tools and software. The demonstration device contains an ARM processor stack, an off-the-shelf FPGA die, and a DRAM memory stack, all assembled onto an active silicon circuit board that functions as an interposer (Fig. 2).

Wafer-Level and Chip-Scale Packaging

To satisfy the needs of today’s mass-market mobile devices, which require the integration of more functions in a smaller form factor like mobile phones and tablets, package-on-package (PoP) technology using flip-chip, chip-scale, and wafer-scale packaging is being used. PoP involves stacking several packaged devices like memory and application-specific processors atop one another within a larger package.

Amkor, for example, uses through-mold vias and fine-pitch flip-chip interconnects with copper pillar bumps to deliver next-generation high-density PoPs. The company is well aware of the need for 3D ICs with TSVs and is actively working on this technology, focusing on developing solutions for the back end of TSV processing.

Flip-chip, wafer-level, and wafer-bump processes are satisfying present market needs until TSVs are perfected for 3D ICs.

“These processes cater to the most demanding needs of mobile and consumer devices,” agrees Wan Choong Hoe, executive vice president and chief operating officer of STATS ChipPAC. The company provides back-end fully integrated packaging and testing solutions that bring products to the market faster, such as package design, bump, probe, assembly, test, and distribution services.

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