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Verilog is a hardware description language that is used in the design of CPLD's, FPGA's and ASIC's.
Detailed Description:
Verilog is a textual language similar in syntax to C. It was first developed by Gateway Design Automation in the early 1980's, its primary purpose being a hardware modelling language.
In 1990, Cadence Design Systems purchased Gateway Design Automation and along with it the rights to Verilog. In the early 1990's Cadence put Verilog into the public domain. Verilog was submitted to the IEEE and became IEEE Std 1364-1995 or just Verilog-95.
More recently the standard has been revised as a result of feedback received from users of Verilog-95. This new standard is IEEE Std 1364-2001 or just Verilog 2001.
Examples:
Example 1: This example demonstrates the basics of creating a Verilog module. Inputs, Outputs and Registers are defined and an always clause provides the counter logic.
DESIGN RESOURCES
FPGA Design 
