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VHDL is a textual language designed specifically for describing complex digital electronic hardware.
Definition of Acronym:
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
Detailed Description:
VHDL is a textual language similar in syntax to Ada. It was developed initially for the United States Department of Defense in order to more consistently and concisely document ASIC's that had been developed for them. Since its first usage as a tool for generating concise documentation, it was soon realised that there was much greater potential. It has been developed into a standard language for FPGA/ASIC design, and has been adopted by many companies worldwide.
Tools were developed that would synthesize VHDL into a netlist of gates suitable for using in CPLD's, FPGA's and ASIC's. Further tools were developed which enabled VHDL to be simulated meaning that a single language could be used from the initial development, through implementing the design into logic, to verifying that the implementation was as required.
Examples:
Example 1: This example demonstrates some basic building blocks of VHDL. An entity and architecture are defined, and a clocked process is used to implement the counter logic.
--
-- Example VHDL counter
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Counter8Bit is
port (
CountValue : out std_logic_vector (7 downto 0);
Clock : in std_logic;
nReset : in std_logic
);
end Counter8Bit;
architecture Rtl of Counter8Bit is
-- Declare internal signals
signal CountTemp : std_logic_vector (7 downto 0);
begin
Count01 : -- Create the 8-bit counter
process (Clock, nReset)
begin
if (nReset = '0') then
CountTemp <= X"00" after 1 ns;
elsif rising_edge (Clock) then
if (CountTemp >= X"FF") then
CountTemp <= X"00" after 1 ns;
else
CountTemp <= CountTemp + X"01" after 1 ns;
end if;
end if;
end process;
CountValue <= CountTemp;
end Rtl;
Example 2: This example demonstrates a method to define a state machine. A type declaration is used to define the states in the state machine, and a clocked process is used to implement the state machine.
--
-- Example VHDL state machine
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TrafficLights is
port (
Red : out std_logic;
Amber : out std_logic;
Green : out std_logic;
Change : in std_logic;
Clock : in std_logic;
nReset : in std_logic
);
end TrafficLights;
architecture Rtl of TrafficLights is
-- Declare types
type TrafficLightsType is (LightRed, LightRedAmber, LightGreen, LightAmber);
DESIGN RESOURCES
FPGA Design 
