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Intel Senior Fellow

Ian Alexander Young

Intel Senior Fellow, Technology and Manufacturing Group
Director, Advanced Circuits and Technology Integration

Intel Senior Fellow Ian Alexander Young, an Intel employee since 1983, is the Director of Advanced Circuits and Technology Integration, Portland Technology Development, in Hillsboro. Ore. He is responsible for defining and developing future circuit directions and optimizing the manufacturing process technology for high-performance microprocessor and communications products.

Starting from development of circuits for a 1Megabit DRAM, he led the design of three generations of SRAM products and manufacturing test vehicles, and developed the original Phase Locked Loop (PLL) based clocking circuit in a microprocessor for the 50MHz Intel486 processor. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel processors through the 0.13um 3.2 GHz Pentium 4, enabling them to leverage transistor speed improvements. This innovative clock circuit was one of the key factors for his promotion to Intel Fellow in 1996. Young has developed a number of optimization metrics for technology development, including the transistor performance metric (FEM) that provided a link between processor performance and basic transistor parameters. After development of a 10Gb/s SONET Serdes transceiver in the 90nm CMOS communications process, he recently led a small group of engineers to produce a world class CMOS Low Noise Amplifier and a wireless LAN RF/baseband Radio in 90nm CMOS.

Young holds 34 patents. He has written more than 10 internal technical publications for the Intel Design Technology Conference, and Intel Technical Journal, as well as numerous external technical publications for IEEE journals.

Young has received three Intel Achievement Awards: In December 1996, "For development of a High Performance P856 Transistor 1.5 Years before Certification;" in April 1992, "For contributions made to the team defining and implementing a unique, cost effective approach to BiCMOS processing for Intel;" and in May 1991, "For the contribution made in the design of an analog PLL for 50-MHz Intel 486 microprocessor chip set. The functional C8 B-step silicon exceeds design requirements."

He has also received divisional awards "for contributions to developing understanding of low power circuit design Best Known Methods and promoting attention to Energy and Speed trade-offs in design throughout the company" and "for exceptional support of LAD Gigabit PHY Analog debug and validation," from Intel's Microprocessor Products Group and Intel's Communications Group.

Born in Melbourne, Australia, in 1951, he received his bachelor's and master's degrees in Electrical Engineering from the University of Melbourne, Australia, in 1972 and 1975. He received his Ph.D. in Electrical Engineering from the University of California, Berkeley in 1978. Prior to Intel, Young worked on analog/digital integrated circuits for Telecommunications at Mostek Corporation, and did some consulting work.

Young serves on the Intel Technology Council and is a member of Intel's Research Council for University research funding. He has served on the technical working group for the development of the International Technology Roadmap for Semiconductors and is a SIA/MARCO Interconnect Focus Center Research Mentor.

Young's contributions in the professional societies outside of Intel have been recognized with his appointment in 1999 as an IEEE Fellow for "contributions to microprocessor design and technology." He currently is serving as the technical program committee chairman of the 2005 International Solid-State Circuits Conference (ISSCC), and is a past chairman of the Symposium on VLSI Circuits. He serves on the Executive Committee for the VLSI Symposia.

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