Since the turn of the century, it has become clear that the data bandwidth capabilities of parallel multidrop buses such as the VMEbus have been increasingly challenged in data-intensive applications. The result has been the launch of what is called the VME Renaissance—an era of VMEbus innovation and performance improvement while maintaining backward compatibility and protecting existing customer investments—to take VMEbus platforms to the next level of performance.
A series of stages were identified for the VME Renaissance. The goal of the first stage was to bolster the bandwidth capabilities of the multidrop VMEbus, and the goal of the second stage was to add switched serial fabrics to VMEbus platforms. The first stage came to fruition in August 2004 with the release of the Tundra TSi148 PCI-X-to-VMEbus bridge chip, which was co-developed with Motorola. The TSi148 implements the 2eSST VMEbus protocol, where “2eSST” stands for two-edge source synchronous transfer. The “source synchronous” part of the name indicates that the transmitter sends data along with a strobe. The “two-edge” portion of the name indicates that transfers are made on both the rising and falling edges of the strobe.
The 2eSST protocol enables products using the TSi148, working in conjunction with Texas Instruments’ SN74VMEH22501 VMEbus transceivers, to provide up 320 Mbytes/s of data bandwidth in properly designed five-row backplanes. This is an 8X increase over the typical 40 Mbyte/s performance of the VME64 protocol. Motorola’s MVME6100 and MVME3100, along with boards from other companies, use the TSi148 and provide a rich ecosystem of 2eSST-enabled products.
A use case example of how 2eSST technology is being considered to improve distributed application performance is the Navy Open Architecture initiative. This initiative has been focused on using Gigabit Ethernet, Data Distribution Service (DDS) and Common Object Request Broker Architecture (CORBA) middleware. 2eSST technology is now being evaluated for this initiative as a high-performance transport that complements Gigabit Ethernet. The next technology beyond 2eSST that could also be leveraged in this initiative is VXS.
VXS – The Second Stage of the Renaissance
The second stage formally began with the formation of the VXS (or VITA 41) working group in the VSO in March 2002. The goals for VXS as outlined at the inception of the working group were to:
• Provide a switched serial interconnect to VMEbus coincident with the VME parallel bus
• Utilize standard open technologies for the switched serial links
• Allow for multiple standard open technologies for the links, but not necessarily at the same time
• Preserve backward compatibility within the VMEbus ecosystem
• Increase the amount of power provided to each VMEbus card
Each of those goals has been achieved through the resultant specifications created by the working group:
VITA 41.0 - VXS Switched Serial Standard (Base Specification)
VITA 41.1 - VXS InfiniBand Protocol Layer Standard
VITA 41.2 – VXS RapidIO Protocol Standard
VITA 41.3 – VXS 1000 Mbit/s Baseband IEEE 802.3 Protocol Layer Standard
VITA 41.4 – VXS PCI Express Protocol Layer Standard
VITA 41.10 – Live Insertion System Requirements for VITA 41 Boards (Trial Use Standard)
VITA 41.11 – VXS Rear Transition Module (RTM) Standard
VITA 41.0-2 and 10 are currently moving toward ANSI standardization. The remaining standards will move to ANSI standardization in early 2006. These standards provide the framework for VXS implementations throughout the embedded computing industry, and a number of platforms have already been released based on them.
VXS – Data Plane and Control Plane
Now that the evolution and scope of the VXS standards have been characterized, how does VXS take VMEbus platforms to the next level of performance? Before tackling this question, it may be helpful to review the data plane and control plane concepts that are well known in the telecommunications industry. The data plane is defined as the portion of network traffic that is used to distribute data between nodes. The control plane is defined as the portion of network traffic used to set up, maintain and terminate data plane connections.
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