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Itanium

Itanium (PAC418)

Implementation Merced: P7 - 418pins FCPGA - PAC418
Instruction set Merced: : CISC - IA64 - MMX - SSE
[info] Intel Itanium processor

CPU info		settings				cache			elec (max)			physics
name	release	speed	FSB	MP	VCore	L1	L2	L3	I	P	T	T	P	D
Itanium 733 (2MB) Merced ?? (?-?-?) 07/2001		733MHz	133MHz DDR	5.5x	?	L1 32KB L2 96KB L3 2MB			71.4A 116.0W 65.0ºC			25.0M 180nm 300mm²
Itanium 733 (4MB) Merced ?? (?-?-?) 07/2001		733MHz	133MHz DDR	5.5x	?	L1 32KB L2 96KB L3 4MB			71.4A 130.0W 65.0ºC			25.0M 180nm 300mm²
Itanium 800 (2MB) Merced ?? (?-?-?) 07/2001		800MHz	133MHz DDR	6.0x	?	L1 32KB L2 96KB L3 2MB			71.4A 116.0W 65.0ºC			25.0M 180nm 300mm²
Itanium 800 (4MB) Merced ?? (?-?-?) 07/2001		800MHz	133MHz DDR	6.0x	?	L1 32KB L2 96KB L3 4MB			71.4A 130.0W 65.0ºC			25.0M 180nm 300mm²

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Itanium2 (PAC611)

Implementation McKinley/Fanwood/Deerfield/Madison: P7 - 611pins FCPGA - PAC611
Instruction set McKinley/Fanwood/Deerfield/Madison: CISC - IA64 - MMX - SSE
[info] Intel Itanium 2 processor

CPU info		settings				cache			elec (max)			physics
name	release	speed	FSB	MP	VCore	L1	L2	L3	I	P	T	T	P	D
Itanium2 900 (1,5MB) McKinley ?? (?-?-?) 07/2002		900MHz	100MHz QDR	9.0x	0.95~1.425V	L1 32KB L2 256KB L3 1,5MB			100.0A 90.0W 85.0ºC			221.0M 180nm 421mm²
Itanium2 1000 (3MB) McKinley ?? (?-?-?) 07/2002		1000MHz	100MHz QDR	10.0x	0.95~1.425V	L1 32KB L2 256KB L3 3MB			100.0A 100.0W 85.0ºC			221.0M 180nm 421mm²
Itanium2 1000 LV (1,5MB) Deerfield ?? (?-?-?) 08/2003		1000MHz	100MHz QDR	10.0x	0.95~1.425V	L1 32KB L2 256KB L3 1,5MB			100.0A 62.0W 85.0ºC			221.0M 180nm 421mm²
Itanium2 1300 (3MB) Madison ?? (?-?-?) 06/2003		1300MHz	100MHz QDR	13.0x	0.95~1.425V	L1 32KB L2 256KB L3 3MB			100.0A 97.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 1300 LV (3MB) Fanwood ?? (?-?-?) 11/2004		1300MHz	100MHz QDR	13.0x	0.95~1.425V	L1 32KB L2 256KB L3 3MB			100.0A 62.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 1400 (4MB) Madison ?? (?-?-?) 06/2003		1400MHz	100MHz QDR	14.0x	0.95~1.425V	L1 32KB L2 256KB L3 4MB			100.0A 91.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 DP 1400 (1,5MB) Madison ?? (?-?-?) 09/2003		1400MHz	100MHz QDR	14.0x	0.95~1.7V	L1 32KB L2 256KB L3 1,5MB			100.0A 99.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 DP 1400 (3MB) Fanwood ?? (?-?-?) ??/2004		1400MHz	100MHz QDR	14.0x	0.95~1.7V	L1 32KB L2 256KB L3 3MB			100.0A 99.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 1500 (4MB) Madison ?? (?-?-?) 06/2003		1500MHz	100MHz QDR	15.0x	0.95~1.425V	L1 32KB L2 256KB L3 4MB			100.0A 107.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 1600 (6MB) Madison ?? (?-?-?) 04/2004		1600MHz	100MHz QDR	16.0x	0.95~1.425V	L1 32KB L2 256KB L3 6MB			100.0A 122.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 1600 (9MB) Madison 9M ?? (?-?-?) 11/2004		1600MHz	100MHz QDR	16.0x	0.95~1.425V	L1 32KB L2 256KB L3 9MB			100.0A 130.0W 83.0ºC			592.0M 130nm 432mm²
Itanium2 DP 1600 (3MB) Fanwood ?? (?-?-?) 11/2004		1600MHz	100MHz QDR	16.0x	0.95~1.7V	L1 32KB L2 256KB L3 3MB			100.0A 99.0W 83.0ºC			410.0M 130nm 374mm²
Itanium2 DP 1600 (3MB) Fanwood ?? (?-?-?) 11/2004		1600MHz	133MHz QDR	12.0x	0.95~1.7V	L1 32KB L2 256KB L3 3MB			100.0A 99.0W 83.0ºC			410.0M 130nm 374mm²

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Itanium2S (PAC611)

Implementation: P7 - 611pins FCPGA - PAC611
Instruction set: CISC - IA64 - MMX - SSE - SSE2
[info] Intel Itanium 2 processor

CPU info		settings				cache			elec (max)			physics
name	release	speed	FSB	MP	VCore	L1	L2	L3	I	P	T	T	P	D
Itanium2 9010 (6MB) Millington ?? (?-?-?) 07/2006		1600MHz VT	133MHz QDR	12.0x	1.087~1.25V	L1 32KB L2 1.25MB L3 6MB			121.0A 75.0W 74.0ºC			?M 90nm ?mm²
Itanium2 9015 (12MB) Montecito ?? (?-?-?) 07/2006		1400MHz Dual Core HT/VT	100MHz QDR	14.0x	1.087~1.25V	L1 64KB L2 2.5MB L3 12MB			121.0A 104.0W 76.0ºC			1720.0M 90nm 596mm²
Itanium2 9020 (12MB) Montecito ?? (?-?-?) 07/2006		1466MHz Dual Core HT/VT	133MHz QDR	11.0x	1.087~1.25V	L1 64KB L2 2.5MB L3 12MB			121.0A 104.0W 76.0ºC			1720.0M 90nm 596mm²
Itanium2 9021 (12MB) Montecito ?? (?-?-?) Q3/2006		1500MHz Dual Core HT/VT	166MHz QDR	9.0x	?	L1 64KB L2 2.5MB L3 12MB			?			1720.0M 90nm 596mm²
Itanium2 9030 (8MB) Montecito ?? (?-?-?) 07/2006		1600MHz Dual Core HT/VT	133MHz QDR	12.0x	1.087~1.25V	L1 64KB L2 2.5MB L3 8MB			121.0A 104.0W 76.0ºC			1720.0M 90nm 596mm²
Itanium2 9031 (8MB) Montecito ?? (?-?-?) Q3/2006		1666MHz Dual Core HT/VT	166MHz QDR	10.0x	?	L1 64KB L2 2.5MB L3 8MB			?			1720.0M 90nm 596mm²
Itanium2 9040 (18MB) Montecito ?? (?-?-?) 07/2006		1600MHz Dual Core HT/VT	133MHz QDR	12.0x	1.087~1.25V	L1 64KB L2 2.5MB L3 18MB			121.0A 104.0W 76.0ºC			1720.0M 90nm 596mm²
Itanium2 9041 (18MB) Montecito ?? (?-?-?) Q3/2006		1666MHz Dual Core HT/VT	166MHz QDR	10.0x	?	L1 64KB L2 2.5MB L3 18MB			?			1720.0M 90nm 596mm²
Itanium2 9050 (24MB) Montecito ?? (?-?-?) 07/2006		1600MHz Dual Core HT/VT	133MHz QDR	12.0x	1.087~1.25V	L1 64KB L2 2.5MB L3 24MB			121.0A 104.0W 76.0ºC			1720.0M 90nm 596mm²
Itanium2 9nnn (32MB) Montvale (Shavano?) H1/2007		1600~2000MHz Dual Core HT/VT	200MHz QDR	8.0~10.0x	?	L1 64KB L2 2.5MB L3 32MB			?			?M 65nm ?mm²

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Itanium "3"

CPU info		settings				cache			elec (max)			physics
name	release	speed	FSB	MP	VCore	L1	L2	L3	I	P	T	T	P	D
Itanium "3" (32MB) Tukwila H1/2008		1666~2500MHz Quad Core	166MHz QDR	10.0~15.0x	?	L1 ?KB L3 32MB			?			?M 65nm ?mm²
Itanium "3" DP Dimona H1/2008		1600~2600MHz Dual Core	200MHz QDR	8.0~13.0x	?	?			?			?M 65nm ?mm²
Itanium "3" Poulson H1/2009		1666~2500MHz Multi Core (max 16 cores)	166MHz QDR	10.0~15.0x	?	?			?			?M 45nm ?mm²

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Itanium Merced

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Itanium2 McKinley/Deerfield

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Itanium2 - Itanium

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Itanium2 - Itanium pins

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