-N64 CART Info-

Bus timing:

ALE_L ALE_H AD
1 1 Cart address (upper 16 bits 0x10xx)
1 0 Cart address (lower 16 bits)

Typical in game bus activity:

AD is valid on the falling edge of ale_x

At most 256 words are transmitted between ALE_L

 

First boot:

The first word read is in the cart header address 0 [0x80371240] which sets the bus speed for subsequent cart access.
byte 0:device latency
byte 1:release
byte 2: pulse width
byte 3:page size
If you set it to 0x8037FF40 then the access timings for loading the boot code at 0x40 in the header would look like the first access at 0, where the read low signal was 4.0us. Can be useful for debugging since all bus activity is slowed down but still functional.

 

Cart Edge Pinout:

GND 1 26 GND
GND 2 27 GND
AD15 3 28 AD0
AD14 4 29 AD1
AD13 5 30 AD2
GND 6 31 GND
AD12 7 32 AD3
/write 8 33 ALE_L
VCC 9 34 VCC
/read 10 35 ALEL_H
AD11 11 36 AD4
AD10 12 37 AD5
12V 13 38 12V
  14 39  
AD9 15 40 AD6
AD8 16 41 AD7
VCC 17 42 VCC
CIC(15)_TO_PIF 18 43 PIF_TO_CIC(14)
1.6MHZ 19 44 JTAG_CLK_R4300
/COLD_RESET 20 45 NMI_R4300
S_DAT 21 46 VIDEO_CLK(pin14_vdc)
GND 22 47 GND
GND 23 48 GND
LAUDIO 24 49 RAUDIO
GND 25 50 GND

VCC=3.3V
looking from the top of the console: pin 1 is left front, pin 26 is left rear


CIC PINOUT

VCC 1 16 VCC
  2 15 DATA_OUT
  3 14 DATA_IN
  4 13 GND
  5 12  
GND 6 11 CLK(~1.5MHZ)
GND 7 10  
GND 8 9 /COLD_RESET


EEPROM PINOUT

GND 1 8 VCC
  2 7  
CLK 3 6 /COLD_RESET
GND 4 5 DATA


CART ROM PINOUT

AD0 1 28 AD15
AD1 2 27 AD14
AD2 3 26 AD13
AD3 4 25 AD12
VCC 5 24 GND
ALEL 6 23 GND
/READ 7 22 VCC
GND 8 21  
ALEH 9 20 /READ
GND 10 19 VCC
AD4 11 18 AD11
AD5 12 17 AD10
AD6 13 16 AD9
AD7 14 15 AD8

PIF Pinout:

CLK(cic/eeprom)(~1.9Mhz) O 1 28   VCC
RC_power_on_reset[1] I 2 27 I /RESET_Switch
DATA_TO_CIC O 3 26   no connect
output_reset_ind[3] O 4 25 O INT2_R4300
DATA_FROM_CIC I 5 24   EEPROM_DAT[2]
/COLD_RESET O 6 23   EEPROM_DAT[2]
NMI_R4300 O 7 22   CONTROLER_4_DAT
enable_high[4] I 8 21   contr_gate
PIF_DAT_CLK(~15Mhz) I 9 20   CONTROLER_3_DAT
GND   10 19   contr_gate
PIF_ADR I 11 18   CONTROLER_2_DAT
GND   12 17   contr_gate
PIF_DATA O 13 16   CONTROLER_1_DAT
GND   14 15   contr_gate

[1]goes high then 160ms later cold_reset high
[2]eeprom dat is driven by both pins
[3]open drain pin driven with RC circuit(unknown/unused function)
[4]some enable output from rambus clock driver (always high)