eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications. The core has been silicon proven in a number of ASIC and FPGA technologies.

Click diagram to
see full detail

  • Configurable 16 or 32-bit, 5-stage pipelined RISC, load-store architecture.
  • Implemented in as little as 8k ASIC gates for minimum 16-bit configuration.
  • Intermixed 16 and 32-bit instructions gives exceptional code density.
  • Uses industrial standard bus architecture for IP interconnection (AMBA APB/AXI).
  • Configurability and custom instructions will deliver a solution with exceptionally low-lower.
  • Applications include sensors, medical, power management, metering, wireless or mobile products.
  • Highly configurable, allowing the processor to be tailored to fit a wide range of applications, on both FPGA and ASIC technology.
  • Performance and code density amongst the very best available
  • Silicon proven
  • License-free SW development using GNU tools
  • Competitive licensing terms
  • Backed up by the EnSilica reputation for quality design services
EnSilica have defined a family of processor cores that demonstrates the versatility of the eSi-RISC configurable architecture to cover a wide range of applications.


EnSilica’s eSi-1600 16-bit CPU core is a low-cost, low-power processor. It offers similar performance to more expensive 32-bit CPUs while having a system cost comparable to that of 8-bit CPUs.

EnSilica’s eSi-3200 32-bit CPU core is particularly suited to embedded control applications.

EnSilica’s eSi-3250 32-bit CPU core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories. The eSi-3250 is suited to a wide range of applications including running complex operating systems such Linux and uClinux.
The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE (Integrated Development Environment). The toolchain is available for both Windows and Linux hosts and is available to use at no cost.

IP Delivery
The eSi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a wide range of ASIC processes and FPGAs. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST.

A selection of AMBA APB peripherals are supplied with the core, including: UART, SPI, I2C™, Timer and GPIO. By using an industry standard bus, a wide range of 3rd party IP cores can also be used.
By utilising EnSilica’s system level design expertise to define the most appropriate configuration for your particular application and then using our design services to integrate the eSi-RISC core within your particular design, you can achieve a truly optimised solution without any of the pain often associated with embedded processor designs.
Discover More

To access the latest White Papers and Application Notes on eSi-RISC go to the 'Download' box below

Contact us...
security code
Enter Security Code *
Copyright © 2001 - 2010 EnSilica Limited. All Rights Reserved.