There are four types of System Resources:
The CPU can only work on one task at a time. In a multitasking operating system the CPU appears to perform multiple tasks simultaneously by quickly switching between them. The Operating System shares CPU time between the programs it is running and the peripheral devices that demand attention.
The alternative to interrupts (called polling) is to have a program in the OS that periodically checks each of the peripheral devices that might require attention. This approach is inefficient as the CPU would be wasting time checking devices that usually did not require attention.
Hardware Interrupts are sent to the CPU over the control bus to indicate that a peripheral device requires attention.
Software Interrupts are special programming instructions used by the Operating System to notify the CPU that a program requires data to be fetched or delivered to a peripheral device. Software Interrupt routines are provided by the OS for performing basic i/o operations in conjunction with the BIOS.
Hardware Interrupts are delivered to the CPU through two interrupt input lines:
A Non Maskable Interrupt cannot be ignored by the CPU.
The IRQ input is "maskable". The CPU can choose to ignore it until it is convenient to handle the interrupt.
The CPU has a single IRQ input but there are many devices demanding the CPU's attention. Two Programmable Interrupt Controllers (PICs) are used to prioritorise and direct all maskable interrupts to the one IRQ input on the CPU. The PICs are integrated into the "chipset" in modern computers.
The PICs have the job of delivering the interrupts to the CPU in "priority order" (the lowest numbered input has the highest priority.
The original PC had only one PIC and IRQ 2, 3, 4, 5, 6 and 7 were connected to the 8 bit ISA bus.
______________
| |
IRQ 0 ------| highest |
IRQ 1 ------| priority |
IRQ 2 ------| |
IRQ 3 ------| |
IRQ 4 ------| PIC |------------> to CPU
IRQ 5 ------| | (one output)
IRQ 6 ------| |
IRQ 7 ------| lowest |
| priority |
|______________|
With the introduction of the 16 bit ISA bus the number of IRQs was increased to 16. A second PIC was added and to maintain compatibility with the original PC, the PICs were cascaded using IRQ 2. IRQ9 was substituted for IRQ2. IRQs 10, 11, 12, 14 and 15 were carried by the 16 bit ISA extension.
ISA bus devices usually required manual configuration to set the interrupt number and other resources for each expansion card. This was done using dip switches or (later) software.
Automatic assignment of system resources to avoid conflicts is done using "Plug and Play" where devices negotiate with the operating system for their prefered values.
With the disappearance of the ISA bus, and the universal use of the PCI bus (and Plug and Play), the "8 and 16 bit" interrupts are available for any device.
A hardware interrupt is issued by a peripheral device, it informs the CPU that the device needs attention and that the CPU should suspend execution of the current task and attend to the device. If the CPU is available (ie. not performing a task with higher priority, such as servicing a higher priority interrupt), it suspends the current task and invokes the interrupt handler for that device.
The role of an interrupt handler is to service the device. An interrupt handler is a similar to a subroutine call. When the handler finishes, the CPU resumes what it was doing before the interrupt occurred.
When a peripheral device signals an interrupt, the PICs will prioritise it. If there are no more important interrupts, the PICs will forward the interrupt to the CPU. If there are more important interrupts, the current interrupt will be held until the more important ones have been handled.
When the CPU gets an interrupt, it saves all its working registers on the stack. The CPU then begins the appropriate Interrupt Service Routine (as requested by the PICs) to handle the interrupt.
This Interrupt Service Routine is pointed to by a 4 byte entry located in the Interrupt Vector table in the bottom 1024 bytes of main memory. The PIC supplies a one byte number appropriate to the interrupt. The CPU multiplies this by four to get the address of the entry in the table.
This scheme is very flexible, it allows the operating system to easily connect a given piece of hardware to any desired Interrupt Service Routine.
When the interrupt has been handled, the CPU will "unstack" its registers and return to the job it was previously doing.
The CPU can generate Software Interrupts through the use of special instructions. These are handled in a similar way to hardware Interrupt Requests, except that the PICs are not involved. Software Interrupts are often used to communicate between a user program and the operating system.
These are addressable locations used by the CPU to communicate with input/output devices. The IO ports act much like memory locations (but in an entirely different "address space") - they can be read and written by the CPU. There are subtle differences though.
In a DMA transfer, the CPU is not directly involved. When a DMA peripheral wishes to transfer data to or from memory, it issues a DMA request signal to a DMA controller. The DMA controller then takes control of the system bus and moves a block of data between the peripheral and main memory without the need for CPU intervention. Providing that CPU does not require the system bus during this time the CPU may continue to process its current task, thus increasing system performance.
The "non DMA" way of performing input and output required the CPU to handle the data twice. In the example (performing input), the CPU first read the I/O device then wrote the data to memory.
The original 8-bit ISA bus had four DMA channels allowing for high-speed transfers between devices and memory. Only three of these channels were made available to the expansion slots. Of these three two were typically used for the hard disk controller and the floppy disk controller, leaving one for use by an additional device.
Since the introduction of the 80286, the ISA bus has supported eight DMA channels (DMA 0 ... DMA 7), seven of which are available to the expansion slots. Like the additional IRQ lines, DMA channels were added by cascading a second DMA controller from the first. As a result, DMA channel 4 is used to cascade channels 0 to 3 to the CPU. Channels 0 to 3 are available for 8-bit transfers (can be used with both 8 and 16 bit ISA cards) and channels 5 to 7 are capable of 16-bit transfers only.
One final method of communicating with a device is the idea of mapping the I/O ports of a device into the normal memory space of the CPU. This allows for the CPU to read from or write to an area of "memory", having the device receive or provide the data. This method can be extremely fast due to the fact that memory bus speeds are typically higher than those of the expansion buses (ISA, PCI, etc.) The most recent example of memory-mapped I/O is the Advanced Graphics Port (AGP.) Unfortunately, there are a number of complexities that need to be overcome when using memory mapped I/O.
When two or more devices attempt to use the same resource (eg. the same IRQ line or I/O Port) ambiguity can occur with unexpected and disastrous results.
Hardware resource conflicts should be avoided.
It is possible for devices to share IRQ lines, however the ISR must determine which device generated the interrupt. Only one of the two devices may be used at any time, otherwise a IRQ conflict will occur.
Memory conflicts are resolved by ensuring that each device uses a different base address and that the area of reserved memory for the device does not extend into another device's memory area.
I/O port address conflicts are resolved in a similar way to memory conflicts. Each device requires a range of port addresses. I/O ports are used to communicate commands and data to/from hardware devices. If two devices attempt to use the same port both devices will receive and provide data when the port is read from or written to.
Like IRQs, DMA channels may also be shared between devices, providing only one device operates at a time. However, if both devices need to operate at simultaneously, separate DMA channels must be used.
There are effectively two types of resource allocation, manual or "Plug and Play". Manual allocation requires that any I/O ports, IRQ lines, DMA channels or Memory Mapped I/O be setup by the user, either by the use of external jumpers (switches) or by the use of a software configuration utility. This is normally the case with all ISA expansion cards.
"Plug and Play" allows for the resources to be automatically distributed by the system BIOS, working together with the Operating System. As a result, no resource conflicts should occur and each device should work in harmony with the rest.
When a PC is first switched on, the Operating System (OS) is not in memory, the hardware to fetch the OS usually is not ready and the memory manager has not been initialised so most of the RAM cannot be used.
The CPU is held in a RESET state until the computer's power supply is working properly. This typically takes about half a second from "switch on". Formally, the power supply circuit sends a Power_Good signal to the "reset" circuitry, bringing the CPU out of the reset state
At this point, the CPU wakes up in
Real Mode ie. it is thinking like an
original 8086 with one megabyte of segmented memory.
The memory manager has not yet been initialised, so the CPU
has no choice.
The CPU goes to a "well known" address in memory - FFFF:0000
hex - to fetch the first instruction.
This means that permanent memory (typically Flash memory)
must be located at this address to ensure there really is
some code there.
FFFF:0000 hex is exactly 16 bytes back from the 1MB boundary.
Since 16 bytes is not enough room to store the code necessary
to start the system, a JMP instruction is
usually used to move back to a block of code located within
the first 1MB of memory.
The boot sequence used when a PC is first powered on (after being completely powered off) is known as a cold boot. This causes all system checks to be performed. When a machine is rebooted, either by pressing the reset switch, telling the operating system to reboot the machine or by pressing CTRL+ALT+DEL a warm boot is performed. In this case less time is spent testing system components as it is assumed that the system has already been running, the full POST has previously been performed and the hardware is already functional.
