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Abstract:

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold voltages. In this paper, we discuss the role of noise in a two state model that mimic the dynamics of standard logic gates and show that the presence of the noise sets a fundamental limit to the computing speed. An optimal idle time interval that minimizes the error probability is derived. ©2007 American Institute of Physics

Notes:

Copyright (2007) American Institute of Physics.
This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics.

The article appeared in Applied Physics Letters (Vol.91, Issue 22), and may be found at: URL: http://link.aip.org/link/?APL/91/224104.
DOI: 10.1063/1.2817968. the Journal issue's table of contents is available at this link: http://link.aip.org/link/?APL/91/22/htmltoc

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