Chipster

At Hot Chips this past week, Intel released more technical details on its coming system-on-a-chip (SoC) processor called Tolapai. Tolapai is Intel's first attempt at an SoC design since its ill-fated "Timna" project a few years back, and when it's launched, it will be their first x86 processor with an on-die memory controller since the 80386EX in 1994. Tolapai is significant because it will be the x86 ISA's next major step into the embedded space, a space currently owned by the PowerPC, ARM, and MIPS ISAs.

A brief look at Tolapai

First, let's look at the basics of the new processor:

• 600MHz, 1 GHz, and 1.2GHz at launch
• 148 million transistors
• 37.5mm x 37.5mm package
• 13-20W TDP
• 65nm process

As we've reported previously, Tolapai will feature a Pentium M-derived processor core. Because the core is a variant of the Pentium M design, it's 32-bit only, but as an embedded part, it doesn't have a real need for 64-bit support.

This processor core is integrated with an on-die northbridge and southbridge that have the following features:

• Memory controller hub
• One-channel 64-bit DDR2 memory controller
• Four-channel DMA controller
• 1x8, 2x4, or 2x1 PCIe

• 2x USB
• 2x SATA
• 2x UART, 37x GPIO
• Timer, RTC, WDT, etc.

Now, this southbridge may seem a little feature-starved—you might expect a set of Ethernet ports or other bus interfaces to hang off of it. But that's because the main I/O hardware is in its own special region of the chip, called the "Acceleration and I/O Complex." The components in this region of the chip have a few special features, but let's first take a look at what they are.

First up is a row of I/O blocks that includes the following:

• 3x gigabit Ethernet MAC
• 1x Local Expansion Bus
• 1x Sync Serial Port (SSP)
• 3x TDM
• 2x Controller Area Network (CAN)

Also in this region of the chip is an accelerator block that's compatible with Intel's QuickAssist Acceleration layer. This accelerator was designed with secure communication in mind, as it features a 256K pool of SRAM, a random number generator, and hardware acceleration for a number of encryption and signature algorithms.

All of the I/O and acceleration hardware blocks in this region of the chip have the ability to talk directly with one another and with the memory controller without passing through the memory controller hub. This is possible because Tolapai has a special bus called FastPath that connects all of the components in the Acceleration and I/O Complex to each other and to the memory controller. (This bus is also connected to the memory controller hub through a bridge.) Because these I/O and acceleration blocks can communicate with each other and with memory very rapidly, the processor's network processing (TCP/IP, SSL, IPsec, etc.) throughput and power efficiency should be significantly improved versus a more traditional design.

So for IPSec applications, a single Tolapai chip could conceivably replace an x86 solution based on four regular chips: a processor, a memory controller hub (MCH), I/O controller hub (ICH), and a crypto accelerator.

Those who've been following Tolapai closely will know that these details were leaked this past January by HKEPC, but the information included above is based on the slide deck from the official Hot Chips announcement. You can see a copy of most of the slides at the Japanese site PC Watch.

The main threat that Tolapai poses initially is to VIA, which right now has the processor that best fits the profile of "embedded x86." Tolapai will take things up a notch in this department, and it may start to crop up in all sorts of form factors in early 2008. Indeed, a Tolapai-based UMPC could take either Windows or OS X down another form factor size, making the current crop of already small UMPC x86 devices look positively bulky.

Update: A few folks have asked about a GPU, so I should discuss this briefly. There's no on-die GPU for this thing, and there are a few good reasons for that. First, Tolapai doesn't need a GPU for the kinds of embedded applications that Intel envisions for it initially, which are mostly networking-related. Second, the industrial and network infrastructure embedded space that Tolapai was designed for is much, much larger in terms of volume than the currently-nonexistent market for UMPCs, so it was out of the question that Intel would design an SoC like this strictly for a form factor that right now is still so unproven, and a GPU is what you'd want in such a design.

If it gets some volume with Tolapai, Intel could cut most of the existing hardware out of the Acceleration and I/O Complex (i.e., the crypto accelerator, the GbE ports, etc.) and possibly turn that into a simple GPU, especially when the part hits the 45nm node. Indeed, the FastPath bus that the Complex sits on would be perfect for graphics, since it would give the GPU a direct line to the memory controller.