Optimized ARM Hard Disk Drive Block Diagram
Hard Disk Drives (HDD) / Solid State Drives (SSD)
Content is clearly exploding. Recent statements from Facebook indicate that the company is adding upwards of 7 petabyes (PB) of storage per month, with in excess of 240 billion photos on file. The need to efficiently store and retrieve audio, video and data files is relevant whether in the cloud or on the client device. Traditionally, the storage of files has been on spinning magnetic media embedded in platforms like PCs, DVRs, game consoles and set-top boxes and today has a market share in excess of 80%. This type of storage remains the approach used for achieving highest density and cheapest storage. However, increasingly, applications with modest storage requirement are adopting Solid State Drive (SSD) technology for the improvements in reliability, power and latency. Through years of working with HDD partners, ARM has perfected its processors, developed leading edge real-time debug solutions and established strong partnerships with key OEMs and silicon partners to meet the needs of storage applications, initially focused on HDD and, more recently, ensuring that the requirements of flash based storage are addressed.
Managing the combination of high rotation speeds, extreme precision requirements of actuators and turbulence caused by fast disk speeds and shock, make hard disk drives (HDD) one of the most challenging real-time control systems. The need to pack more data per inch and increase the speed with which data is read/written from/to the disk, is driving processor performance requirements ever higher. All this must be accomplished inside tight power and cost budgets. In these systems, the approach most system designers have taken is to dedicate one processor core to manage the communication to the host and one to controlling the magnetic head used to read/write data from the platter.
Although these include no spinning magnetic media, processor performance requirements are equally challenging for SSDs. There is an approach of using multiple processors, splitting the tasks of managing data read and writes along with wear leveling algorithms (ensuring different areas of the flash are written to, in order to prolong the useful life of the disk).
HDD and SSD systems both require processor cores that can deliver very high levels of performance inside tight guaranteed real-time constraints. In the HDD space, companies have typically implemented an asymmetric multiprocessing environment using Cortex-R4 and (increasing Cortex-R5 or Cortex-R7) due to the real-time performance and ECC support. For SSD platforms, there is a more diverse range of approaches, with some customers dedicating a Cortex-M series processor for each memory channel, while others utilize a more powerful Cortex-R5 processor to manage multiple channels.
OEMs value the unparalleled software tools and debug infrastructure around the ARM architecture that allows them to rapidly evolve and deploy products from generation to generation. The Cortex-R4 processor architecture features the appropriate balance between processor performance, and real-time response times, with a high degree of debugability to support the AMP chip architectures appearing now to address this market.
ARM Physical IP libraries and Power Management Kits are designed to reduce cost and power usage by minimizing silicon area and leakage, while optimizing performance ensure that the overall device minimizes power leakage. In addition, Physical IP Embedded Memory create high density on-chip memories on a SoC that can exceed 4Mbyte today. The resultant memories, optimized for both performance and power, offering fault tolerance to increase manufacturing yields. Physical IP DDR PHY enables robust off-chip memory interface performance at high clock-speed and low power.
Processors
System IP
- AMBA AXI Network Interconect
- CoreLink Level 2 Cache Controllers
- CoreLink Memory Controllers
- CoreSight
