Jitter Attenuating Clocks/Jitter Cleaners Silicon Labs' jitter attenuating clock products generate any output frequency from any input frequency with ultra-low jitter (0.3 ps rms). These devices lock to a jittered recovered clock, backplane reference or local crystal/clock, provide jitter/wander filtering and frequency translation and produce any rate output frequencies to drive high speed SerDes, FPGAs and PHYs. Download the Clock and Oscillator Product Selector Guide Download the Broadcast Video Timing Solutions Guide
Featured Product Si5328 SyncE Jitter Attenuating Clock Multiplier NEW Silicon Labs' Si5328 is the industry’s lowest jitter, most frequency flexible SyncE clock, making it ideal for Ethernet PHYs from GbE to 100 GbE. The Si5328 is fully compliant with ITU-T G.8262 Synchronous Ethernet clock requirements, including EEC Option 1 and EEC Option 2. The device supports a 0.1 Hz PLL bandwidth, eliminating the need for discrete timing card PLLs in some system configurations.
Any-Frequency Jitter Attenuating Clocks Part Number # of PLLs Control Clock Inputs / Outputs PLL Bandwidth Applications Si5315 1 Pin 2/2 60 Hz–8 kHz OTN (10G/40G/100G) SONET/SDH Line Cards 10G Switches/Routers Synchronous Ethernet Broadband Infrastructure Broadcast Video Test and Measurement Military/Aerospace Medical Imaging Si5316 1 Pin 2/1 100 Hz–8 kHz Si5317 1 Pin 1/2 60 Hz–8 kHz Si5319 1 I2C/SPI 1/1 60 Hz–8 kHz Si5323 1 Pin 2/2 60 Hz–8 kHz Si5324 1 I2C/SPI 2/2 4 Hz–525 Hz Si5326 1 I2C/SPI 2/2 60 Hz–8 kHz Si5327 1 I2C/SPI 2/2 4 Hz–525 Hz Si5328 1 I2C/SPI 2/2 0.1 Hz, 1 Hz–10 Hz Si5366 1 Pin 4/5 60 Hz–8 kHz Si5368 1 I2C/SPI 4/5 60 Hz–8 kHz Si5369 1 I2C/SPI 4/5 4 Hz–525 Hz Si5374 4 I2C 8/8 4 Hz–525 Hz Si5375 4 I2C 4/4 60 Hz–8 kHz Si5376 4 I2C 8/8 60 Hz–8 kHz
Standards Compliance Application Standards-Compliant Solution SONET/SDH up to OC-192 Meets Telcordia GR-253 jitter generation, jitter transfer and jitter tolerance specifications Optical Transport Networking (OTN) Supports 10G, 40G and 100G clocking applications Carrier Ethernet Fully compliant with G.8262, including EEC Option 1 and Option 2 (Si5328) Meets G.8262 requirements when paired with a Stratum 3 timing card clock (Si5315) Datacomm Meets the jitter requirements for GbE, 10 GbE and 40 GbE PHYs Broadcast Video Meets the jitter requirements for HD SDI, 3G SDI and 6G SDI with >80% margin
These devices leverage patented DSPLL® technology to eliminate external VCXOs and loop filters while improving immunity to board-level noise. Other benefits include: Highly consistent, repeatable phase noise and jitter across process, voltage and temperature. In-system reconfigurable and require no BOM changes to support different frequencies or loop bandwidths. Supports line card features: hitless switching and holdover, making them ideal for SONET/SDH and packet-based networks.
Online Utilities Clocks Parametric Search Find clocks fast by defining your application and technical requirements Buffer Parametric Search Oscillator Parametric Search Custom Timing Design Specify a custom clock, oscillator or clock tree design in minutes Convert Phase Noise>Jitter Easily convert phase noise to phase jitter, period jitter, and cycle-to-cycle jitter