Some time ago a friend handed me a bare J-11 chip. It had been pulled from some system on the way to scrap, presumably just because it was a pretty object. A few pins were bent and it had not been static-protected - what sort of handling it had seen was unknown. I wondered whether it was now anything more than a pretty object.

The J-11 (more properly the DCJ11, aka "Jaws") was one of the last gasps of the PDP-11 - a CMOS microprocessor implementation of the PDP-11/70. It was two chips actually, mounted on a single 60-pin, over-wide, DIP ceramic carrier. The J-11 was developed in the early 1980s. It was introduced in the PDP-11/73 in 1983/84. Although this was at the end of the heyday of the PDP-11, it saw a relatively long production life, being produced till sometime into the 1990s. The unit here has a date code from 1987.

I had a recollection of hearing that these microprocessors had an ODT (Octal Debugging Technique) built into the microcode. ODT is a simple ASCII-based console monitor. The question was what would be the minimal hardware setup that would allow one to talk to the ODT. In theory, it should just be a matter of appropriately wiring up a UART to the J-11.

Contents (this page):

Sub-pages:

References / External Links:

The Hack

The PDP-11/HACK is a minimal system built around the J-11, enough to check the chip for basic operation. Implemented with just 12 or 13 ICs, it has 16 KB of memory and a single I/O device - the console serial port. I'll hazard a guess this is the lowest-IC-count 'real' PDP-11 system - that is, leaving aside emulations on modern system-on-a-chip hardware or FPGA implementations. File it under silly-chip-tricks.

Thankfully, a datasheet for the J-11 is available online at bitsavers.org. In short: a little reading of the J-11 User's Guide, a little designing, a little breadboarding, and voila: a functioning PDP-11. The schematic is linked above.

The Console Device

The ODT expects to see a 4-register device at addresses 17777560-17777566 in the I/O space. Normally this facility was provided by a DEC "DLART-compatible" device, DEC made the DC319-AA UART for the task. I didn't have a DC319 and I expect they're somewhat difficult to come by. Instead, I pulled a 6402 UART out of the parts bin, primarily because the 6402 is hardware configurable, so no boot-time programmatic access is required to load registers to configure it. The 6402 is also single-supply, making it mildly preferable over other hardware-configured UARTs such as the 1402 or AY-5-1013, although they too should do the job.

Just a few TTL gates were needed to make the 6402 appear on the bus as the 4 device registers with enough functionality to make the ODT happy. The small PC board seen at the top in the breadboard photos is a baud-rate generator from some unknown piece of equipment, used here for the UART serial clock. Something simpler could be done with just one IC, such as a CMOS 4060. A MAX-232 provides the RS-232 interface.

Bus Protocol

A couple more TTL chips were needed for an address latch for the multiplexed data/address lines and some bus protocol. The BS0/1 lines from the J-11 do some pre-decoding to distinguish memory and I/O bus operations. This considerably simplifies the external address decoding required.

Working..

The first version had no memory, but it talked to the ODT and was enough to show the chip was working at some level. Next, two 6264 8K*8 static RAM chips were added to provide 8KW/16KB of memory. Two simple test programs were manually assembled, entered via the ODT and successfully executed (once I had reacquainted myself with the PDP-11 instruction set to the point of recalling that branch offsets are relative to the following instruction, not the branch instruction).

There is a little confusion around the maximum clock rate for the J-11. The 1983 Preliminary User's Guide specifies a max clock rate of 15 MHz. Bob Supnik's article (link above) suggests they were achieving only around 4.5 MHz in that time frame. Other sources indicate that later units went to 18 MHz. The 11/HACK ran with crystals of 2, 4, 8 and 11 MHz, but did not function with a 14 MHz crystal though the on-chip oscillator was still going. The limit is likely more of a consequence of the rest of the system rather than the J-11.

Test Programs

//*** Note: Ensure the PSW is appropriate before running, 000340 is good.

//**************************************************************************
//***	PDP-11 Test #1 - Load R5 and return to ODT

000	012705			MOV #125252,R5
002	125252
004	000000			HALT


//**************************************************************************
//***	PDP-11 Test #2 - Repeatedly output a character to the console port

010	032737		loop	BIT #200,(#177564)	// check bit-7/ready of xmt status reg
012	000200
014	177564
016	001774			BEQ loop		// busy-loop while bit-7 is 0

020	012737			MOV #102,(#177566)	// send ASCII B to xmt data reg
022	000102
024	177566
026	000770			BR loop			// again

Update

2014 Nov:
Peter Schranz in Switzerland had a J11 kicking around too and has also made a PDP-11/HACK. Here's the message and photo he sent. He got the IC count down to 9, while increasing the memory to 128KW, by using a GAL for the glue logic and larger SRAMs. The alterations also allow it to run at 18MHz.