Abhoriel, if I replaced all combinations of 0x0008AF2F (800 MHz) to 0x00CA9A3B (1000 MHz) in the kernel, is it OK?
I'm looking at the new kernel now. There are 3 references to 800MHz (0x0008AF2F) and they are each within a different clk structure.
The first structure is called a9_clk, which is the one we want to change.
The second is called "clk_sys_pl" and the third "clk_misc_pl". I have no idea what these two do (I've read a bit of old amlogic kernel source (we cant use this source to compile a kernel unfortunately, its too old
) and I'm still not certain - not an expert at this).
clk_sys_pl.rate gets set to double a9_clk.rate at initialisation however.
clk_other_pl is related to yet another clock called "clk81". Not sure what this is for either, but it seems to be for an MPEG decoder or something..
We need the source code
But, I recommend changing the first value and leaving the others how they are. see what happens