MIPS: ingenic: enable BTB lookups for short loops

The XBurst core by default attempts to avoid branch target buffer lookups by detecting & special casing loops. However when short loops (<= 4 instructions) are encountered this logic ends up introducing extra interlock cycle penalties & slowing performance. Setting bit 4 of the Config7 register disables this logic, restoring the performance of short loops at the cost of increased BTB contention when running longer loops. TODO: benchmark this with something more meaningful than bogomips TODO: which other SoCs does this apply to? Signed-off-by: Paul Burton <paul.burton@imgtec.com>
paulburton · Mar 4, 2015 · 0d72377bd615d00e99733adc0d37e6a2373fcde7 · 0d72377
1 parent ed40f32
commit 0d72377bd615d00e99733adc0d37e6a2373fcde7
Unified Split

Showing with 10 additions and 0 deletions.

+4 −0 arch/mips/include/asm/mipsregs.h

+6 −0 arch/mips/kernel/cpu-probe.c
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
@@ -580,6 +580,9 @@
 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+  
+/* Ingenic Config7 bits */
+  
+#define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
+  
+
 /* MAAR bit definitions */
 #define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 #define MIPS_MAAR_ADDR_SHIFT	12
@@ -2006,6 +2009,7 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+  
+__BUILD_SET_C0(config7)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
@@ -1312,6 +1312,12 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		panic("Unknown Ingenic Processor ID!");
 		break;
 	}
+  
+
+  
+	switch (c->processor_id & PRID_COMP_MASK) {
+  
+	case PRID_COMP_INGENIC_4780:
+  
+		set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
+  
+		break;
+  
+	}
 }
 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)