On-Chip Networks Bibliography (not maintained since 2007)

To contribute new (or correct mistakes in current) BibTeX entries please email: Robert.Mullins@cl.cam.ac.uk The cite key format is [FirstAuthorLastName:Year:KeyPhrase] where KeyPhrase is usually the first letters of the first three words in the title e.g. [Jones:2006:OCN] (Don't worry too much if your files are not in this format - I can make the necessary changes automatically). Please also indicate where the paper should be added in the bibliography browser tree (or suggest an appropriate new branch). If you wish to cite the bibliography itself use 'cl-noc-bib'. Many thanks to everyone who has contributed entries. For other resources take a look at the On-Chip Network Research Resources Page Other relevant bibliographies: Globally-Asynchronous Locally-Synchronous (GALS) Bibliography Pausible, stretchable and data-driven clock designs. On-Chip Communication Bibliography at OCP-IP

Not updated now, 100+ pubs. per year after 2005...

Bibliography Browser (needs updating!)

The Bibliography

[1 — Ahonen:2004:ABF]

Tapani Ahonen et al. A brunch from the coffee table – case study in NoC platform design. In J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, editors, Interconnect-Centric Design for Advanced SoC and NoC, pages 425–453. Kluwer Academic Publishers, 2004.

[2 — Ahonen:2004:TOF]

Tapani Ahonen, David Sigüenza Tortosa, and Jari Nurmi. Topology optimization for application-specific networks-on-chip. In Proc. 6th International Workshop on System Level Interconnect Prediction, Paris, France, 2004.

[3 — Ainsworth:2007:OCP]

Thomas Ainsworth and Timothy Pinkston. On characterizing performance of the Cell broadband engine element interconnect bus. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[4 — Akerlund:2005:IOA]

Daniel Åkerlund. Implementation of a 2x2 NoC with wishbone interface. Master's thesis, School for Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden, November 2005.

[5 — Alho:2003:IOI]

Mikko Alho and Jari Nurmi. Implementation of interface router IP for Proteo network-on-chip. In Proc. The 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, 2003.

[6 — Alho:2003:SBI]

Mikko Alho and Jari Nurmi. Switch-based interface router IP for proteo network-on-chip. In Proc. The 1st Northeast Workshop on Circuits and Systems NEWCAS, Montreal, Canada, 2003.

[7 — Ali:2005:CFF]

M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand. Considerations for fault-tolerant network on chips. In Proc. of the 17th Intl. Conf. on Microelectronics (ICM), 2005.

[8 — Amde:2005:AOC]

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno. Asynchronous On-Chip Networks. IEE Proceedings Computers and Digital Techniques, 152(02), March 2005.

[9 — Andrzejewski:2005:ABE]

Marek Andrzejewski. AMBA bus emulation in the Nostrum NoC using best effort communication. Master's thesis, School for Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden, December 2005.

[10 — Angiolini:2006:CAN]

F Angiolini, L Benini, P Meloni, L Raffo, and S Carta. Contrasting a NoC and a traditional interconnect fabric with layout awareness. In In Proc. Design, Automation and Test in Europe (DATE), March 2006.

[11 — Ascia:2006:MMF]

Giuseppe Ascia, Vincenzo Catania, and Maurizio Palesi. Multi-objective mapping for mesh-based NoC architectures. In Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 182–187, Stockholm, Sweden, September 8–10 2004.

[12 — Ascia:2006:NOP]

Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, and Davide Patti. Neighbors-on-Path: A new selection strategy for on-chip networks. In Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pages 79–84, Seoul, Korea, October 2006.

[13 — Avasare:2005:CEF]

P. Avasare, V. Nollet, J-Y. Mignolet, D. Verkest, and H. Corporaal. Centralized end-to-end flow control in a best-effort network-on-chip. In EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded software, pages 17–20, New York, NY, USA, 2005. ACM Press.

[14 — Awasthi:2006:ETD]

M. Awasthi and R. Balasubramonian. Exploring the Design Space for 3D Clustered Architectures. In Proceedings of the 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, October 2006.

[15 — Bainbridge:2002:CAD]

W. J. Bainbridge and S. B. Furber. CHAIN: A Delay Insensitive CHip Area INterconnect. IEEE Micro special issue on Design and Test of System on Chip, 142, No.4.:16–23, September 2002.

[16 — Bainbridge:2004:TDA]

L. A. Plana W. J. Bainbridge and S. B. Furber. The design and test of a smartcard chip using a CHAIN self-timed network-on-chip. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, volume 3, page 274, February 2004. ISBN 0769520855.

[17 — Bainbridge:2003:DIP]

W. J. Bainbridge, W. B. Toms, D. A. Edwards, and S. B. Furber. Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes. In Proceedings of the 9th IEEE Intl Symp. on Asynchronous Circuits and Systems, pages 132–140, May 2003.

[18 — Balasubramonian:2003:DMT]

R. Balasubramonian, S. Dwarkadas, and D. H. Albonesi. Dynamically Managing the Communication-Parallelism Trade-Off in Future Clustered Processors. In Proceedings of ISCA-30, pages 275–286, June 2003.

[19 — Balasubramonian:2005:MWM]

R. Balasubramonian, N. Muralimanohar, K. Ramani, and V. Venkatachalapathy. Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. In 11th International Symposium on High-Performance Computer Architecture (HPCA-11), February 2005.

[20 — Balasubramonian:2006:LWP]

R. Balasubramonian, N. Muralimanohar, K. Ramani, L. Cheng, and J. Carter. Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro, 26(6), November/December 2006.

[21 — Balfour:2006:DTF]

James Balfour and William J. Dally. Design tradeoffs for tiled CMP on-chip networks. In Proceedings of the 20th ACM International Conference on Supercomputing (ICS), June 2006.

[22 — Balkan:2004:AMP]

Aydin O. Balkan, Gang Qu, and Uzi Vishkin. Arbitrate-and-Move Primitives for High Throughput On-Chip Interconnection Networks. In Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS), volume II, pages 441–444, Vancouver, May 2004.

[23 — Balkan:2006:MOT]

Aydin O. Balkan, Gang Qu, and Uzi Vishkin. A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing. In Proceedings of the Application-Specific Systems, Architectures and Processors (ASAP), pages 73–80, 2006.

[24 — Balkan:2007:LAD]

Aydin O. Balkan, Michael N. Horak, Gang Qu, and Uzi Vishkin. Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing. In Proc. IEEE Symp. on High Performance Interconnection Networks (Hot Interconnects), Stanford University, CA, August 2007.

[25 — Banerjee:2004:APA]

Nilanjan Banerjee, Praveen Vellanki, and Karam S. Chatha. A power and performance model for network-on-chip architectures. In Proc. of the Design, Automation and Test in Europe Conference (DATE), 2004.

[26 — Banerjee:2007:PEE]

Arnab Banerjee, Robert Mullins, and Simon Moore. A power and energy exploration of network-on-chip architectures. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[27 — Bartic:2003:HSN]

T. A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Highly scalable network on chip for reconfigurable systems. In Proc. Intl. Symp. on System-on-Chip, pages 79–82, 2003.

[28 — Bartic:2006:NOC]

T. A. Bartic, D. Desmet, J-Y. Mignolet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, J. Miller, and F. Robert. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. In Field Programmable Logic and Application, volume 3203/2004 of Lecture Notes in Computer Science, pages 637–647. Springer Berlin / Heidelberg, 2004. (doi:10.1007/b99787)

[29 — Bartic:2005:TAN]

T. A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Topology adaptive network-on-chip design and implementation. IEE Proceedings - Computers and Digital Techniques, 152(4):467–472, July 2005.

[30 — Beigne:2006:DOO]

E. Beigné and P. Vivet. Design of on-chip and off-chip interfaces for a GALS noC architecture. In 12th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC'06), pages 172–183, 2006.

[31 — Beigne:2005:AAN]

Edith Beigne, Fabien Clermidy, Pascal Vivet, Alain Clouard, and Marc Renaudin. An Asynchronous NOC Architecture Providing Low Latency Service and its Multi-Level Design Framework. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005.

[32 — Bengtsson:2006:OLT]

Tomas Bengtsson, Artur Jutman, Shashi Kumar, Zebo Peng, and Raimund Ubar. Off-line testing of delay faults in NoC interconnects. In Proc. 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD), September 2006.

[33 — Bertozzi:2004:XAN]

Davide Bertozzi and Luca Benini. Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip. IEEE Circuits and Systems Magazine, 4, 2004.

[34 — Bertozzi:2002:LPE]

D. Bertozzi, L. Benini, and G. De Micheli. Low power error resilient encoding for on-chip data buses. In Proceedings Design, Automation and Test in Europe Conference and Exhibition, pages 102–109, 2002.

[35 — Bertozzi:2002:EEA]

D. Bertozzi, L. Benini, and B. Ricco. Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding. In IEEE International Symposium on Circuits and Systems, pages 93–96, 2002.

[36 — Bertozzi:2005:ECS]

D. Bertozzi, L. Benini, and G. De Micheli. Error Control Schemes for On-chip Communication Links: the energy-reliability trade-off. IEEE Transactions on CAD, 24(6):818–831, 2005.

[37 — Bertozzi:2005:NSF]

D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli. NoC Synthesis Flow for Customized Domain Specific Mutliprocessor Systems-on-Chip. IEEE Transactions on Parallel and Distributed Systems, 16(2):113–129, 2005.

[38 — Bhojwani:2003:ICW]

P. Bhojwani and R. Mahapatra. Interfacing cores with on-chip packet-switched networks. In Proc. of VLSI Design, January 2003.

[39 — Bhojwani:2006:CNI]

P. Bhojwani and R. Mahapatra. Core network interface architecture and latency constrained on-chip communication. In Proc. of Int. Symp. on Quality Electronic Design (ISQED), 2006.

[40 — Bhojwani:2007:AII]

P. Bhojwani and R. Mahapatra. An infrastructure-IP for online testing of network-on-chip based SoCs. In Proc. of Int. Symp. on Quality Electronic Design (ISQED), pages 867–872, March 2007.

[41 — Bhojwani:2007:ARP]

P. Bhojwani and R. Mahapatra. A robust protocol for Concurrent On-Line Test (COLT) of NoC-based systems-on-a-chip. In Proc. of ACM/IEEE Design Automation Conference (DAC), 2007.

[42 — Bhojwani:2005:AHF]

P. Bhojwani, R. Mahapatra, E. J. Kim, and T. Chen. A heuristic for peak power constrained design of Network-on-Chip (NoC) based multimode system. In Proc. of VLSI Design, January 2005.

[43 — Bhojwani:2006:FEC]

P. Bhojwani, R. Singhal, G. Choi, and R. Mahapatra. Forward error correction for on-chip networks. In Proc. of Workshop for Unique Chips and Systems (UCAS-2), March 2006.

[44 — Bhojwani:2003:MMS]

Praveen Bhojwani. Mapping multimode system communication to a network-on-a-chip (NoC). Master's thesis, August 2003.

[45 — Bjerregaard:2006:ASO]

Tobias Bjerregaard and Shankar Mahadevan. A survey of research and practices of network-on-chip. ACM Computing Surveys, 38(1), 2006.

[46 — Bjerregaard:2004:VCD]

Tobias Bjerregaard and Jens Sparsø. Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip. In Proceedings of the IEEE Norchip Conference (NORCHIP 2004). IEEE, 2004.

[47 — Bjerregaard:2005:ASD]

Tobias Bjerregaard and Jens Sparsø. A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-chip. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005.

[48 — Bjerregaard:2005:ARA]

Tobias Bjerregaard and Jens Sparsø. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In Proceedings of Design, Automation and Testing in Europe Conference 2005 (DATE05). IEEE, 2005.

[49 — Bjerregaard:2004:ACL]

Tobias Bjerregaard, Shankar Mahadevan, and Jens Sparsø. A channel library for asynchronous circuit design supporting mixed-mode modeling. In Proceedings of the Fourteenth International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS2004, pages 301–310, 2004.

[50 — Bjerregaard:2005:AOC]

Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, and Jens Sparsø. An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip. In Proceedings of International Symposium on System-on-Chip 2005. IEEE, 2005.

[51 — Bjerregaard:2005:TMC]

Tobias Bjerregaard. The MANGO clockless network-on-chip: Concepts and implementation. PhD thesis, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby, 2005.

[52 — Bolotin:2004:CCI]

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. Cost considerations in network on chip. Integration-The VLSI Journal, Special issue: Networks on chip and reconfigurable fabrics, 38, Issue 1:19–42, October 2004.

[53 — Bolotin:2004:QQA]

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture, special issue on Network on Chip, 50:105–128, February 2004.

[54 — Bolotin:2004:AHE]

E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, and A. Kolodny. Automatic hardware-efficient SoC integration by QoS network on chip. In Proc. of the 11th IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), pages 483–486, December 2004.

[55 — Bolotin:2007:PPN]

Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, and Avinoam Kolodny. The power of priority: NoC based distributed cache coherency. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[56 — Bononi:2006:SAA]

L Bononi and N Concer. Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. In In Proc. Design, Automation and Test in Europe (DATE), March 2006.

[57 — Bourduas:2007:HRM]

Stephan Bourduas and Zeljlko Zilic. A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[58 — Briere:2005:HMO]

Matthieu Briére, Emmanuel Drouard, Fabien Mieyeville, David Navarro, and Ian O'Connor Frédéric Gaffiot. Heterogeneous Modelling of an Optical Network-on-Chip with SystemC. In 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), pages 10–16, 2005.

[59 — Brinkmann:2002:OCI]

A. Brinkmann, J.-C. Niemann, I. Hehemann, D. Langen, and M. Porrmann andU. Ruckert. On-Chip Interconnects for Next Generation System-on-Chips. In In Proc. of the 15th Annual IEEE International ASIC/SOC Conference, September 2002.

[60 — Bystrov:2000:PA]

A. Bystrov, D. J. Kinniment, and A. Yakolev. Priority arbiters. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 2000.

[61 — Campobello:2006:GNO]

G Campobello, M Castano, C Ciofi, and D Mangano. GALS networks on chip: new solutions for asynchronous delay-insensitive links. In In Proc. Design, Automation and Test in Europe (DATE), March 2006.

[62 — Caputa:2006:A3G]

Peter Caputa and Christer Svensson. A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. In Proc. of 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), pages 117–122, 2006.

[63 — Carloni:2002:CWL]

L. P. Carloni and A. L. Sangiovanni-Vincentelli. Coping with latency in SoC design. IEEE Micro, Special Issue on Systems on Chip, 22(5):12, October 2002.

[64 — Carrion:1996:DET]

C. Carrion and A. Yakovlev. Design and evaluation of two asynchronous token ring adapters. Technical Report TR. no. 562, Department of Computing Science, University of Newcastle upon Tyne, October 1996.

[65 — Castells:2006:AVP]

David Castells-Rufas, Jaume Joven, and Jordi Carrabina. A validation and performance evaluation tool for ProtoNoc. November 2006.

[66 — Chan:2005:NEM]

Jeremy Chan and Sri Parameswaran. NoCEE: Energy macro-model extraction methodology for network on chip routers. In Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD), 2005.

[67 — Chang:2001:RWI]

M. F. Chang, V. P. Roychowdhury, Liyang Zhang, and Hyunchol Shin; Yongxi Qian. RF/wireless interconnect for inter- and intra-chip communications. Proceedings of the IEEE, 89(4):456–466, April 2001.

[68 — Chang:2003:NSO]

R. Chang, N. Talwalkar, C. Yue, and S. Wong. Near Speed-of-Light Signaling Over On-Chip Electrical Interconnects. IEEE Journal of Solid-State Circuits, 38(5):834–838, May 2003.

[69 — Chang:2005:ARB]

M.-C. F. Chang, I. Verbauwhede, C. Chien, Zhiwei Xu Jongsun Kim, J. Ko, Qun Gu, and Bo-Cheng Lai. Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications. IEEE Trans. on Electron Devices, 52(7):1271–1285, July 2005.

[70 — Chen:2007:LLL]

Shuming Chen and Xiangyuan Liu. A low-latency and low-power hybrid insertion methodology for global interconnects in VDSM designs. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[71 — Chen:2002:PPO]

H. Chen, B. Yao, F. Zhou, and C. Cheng. Physical Planning of On-Chip Interconnect Architectures. In Proceedings of International Conference on Computer Design, pages 30–35, 2002.

[72 — Chen:2006:CDC]

Guangyu Chen, Feihui Li, and Mahmut Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL), pages 194–205, New York, NY, USA, 2006. ACM Press.

[73 — Cheng:2005:WMF]

L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, and J. Carter. Wire Management for Coherence Traffic in Chip Multiprocessors. In Proceedings of the 6th Workshop on Complexity-Effective Design, held in conjunction with ISCA-32, June 2005.

[74 — Cheng:2006:ICP]

L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, and J. Carter. Interconnect-Aware Coherence Protocols for Chip Multiprocessors. In Proceedings of 33rd International Symposium on Computer Architecture (ISCA-33), pages 339–350, June 2006.

[75 — Chou:2008:CAM]

Chen-Ling Chou and R. Marculescu. Contention-aware application mapping for network-on-chip communication architectures. In Computer Design, 2008. ICCD 2008. IEEE International Conference on, pages 164–169, October 2008. (doi:10.1109/ICCD.2008.4751856)

[76 — Chou:2008:EAP]

Chen-Ling Chou, U. Y. Ogras, and R. Marculescu. Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 27(10):1866–1879, October 2008. (doi:10.1109/TCAD.2008.2003301)

[77 — Ciordas:2004:AEB]

Calin Ciordas, Basten, Twan, Andrei Radulescu, Kees Goossens, and Jef van Meerbergen. An event-based network-on-chip monitoring service. In Proceedings of High-Level Design Validation and Test Workshop (HLDVT), pages 149–154, November 2004.

[78 — Ciordas:2005:AEB]

Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, and Jef van Meerbergen. An event-based network-on-chip monitoring service. ACM Transactions on Design Automation of Electronic Systems, 10(4):702–723, October 2005. HLDVT'04 Special Issue on Validation of Large Systems.

[79 — Ciordas:2006:NMI]

Calin Ciordas, Kees Goossens, Andrei Radulescu, Kees Goossens, and Twan Basten. NoC monitoring: Impact on the design flow. In Proc. Int'l Symposium on Circuits and Systems (ISCAS), May 2006.

[80 — Cohen:2008:SAN]

Itamar Cohen, Ori Rottenstreich, and Isaac Keslassy. Statistical approach to NoC design. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2008.

[81 — Cota:2004:TSF]

Chunsheng Liu Cota, H Sharif, and Dhiraj Pradhan. Test scheduling for network-on-chip with BIST and precedence constraints. In Proc. of the IEEE Intl. Test Conference, pages 1369–1378, November 2004.

[82 — Alessandro:2006:MRP]

Crescenzo D'Alessandro, Delong Shang, Alex Bystrov, Alex Yakovlev, and Oleg Maevsky. Multiple-rail phase-encoding for NoC. In 12th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC'06), pages 107–116, 2006.

[83 — Dalessandro:2007:NCS]

Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment, and Alex Yakovlev. NoC communication strategies using time-to-digital conversion. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[84 — Dally:2001:RPN]

William J. Dally and Brian Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. of the 38th Design Automation Conference (DAC), June 2001.

[85 — Dally:2003:PAP]

William J. Dally and Brian Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.

[86 — Dally:1987:WEV]

W. J. Dally. Wire-Efficient VLSI Multiprocessor Communication Networks. In Paul Losleben, editor, Proceedings of the Stanford Conference on Advanced Research in VLSI. MIT Press, March 1987.

[87 — Dally:1990:VCF]

William J. Dally. Virtual-Channel Flow Control. In Proc. of the 17th Annual International Symposium on Computer Architecture (ISCA), pages 60–68, Seattle, Washington, May 1990.

[88 — Micheli:2002:NOC]

G. de Micheli and L. Benini. Networks on chip: A new paradigm for systems on chip design. In DATE '02: Proceedings of the conference on Design, automation and test in Europe, page 418, Washington, DC, USA, 2002. IEEE Computer Society.

[89 — Dielissen:2003:CAI]

John Dielissen, Andrei Radulescu, Kees Goossens, and Edwin Rijpkema. Concepts and implementation of the Philips network-on-chip. In IP-Based SOC Design, November 2003.

[90 — Diguet:2007:NCS]

Jean-Philippe Diguet, Guy Gogniat, Samuel Evain, Romain Vaslin, and Emmanuel Juin. NOC-centric security of reconfigurable SoC. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[91 — Dobkin:2005:AAR]

R. Dobkin, V. Vishnyakov, E. Friedman, and R. Ginosar. An asynchronous router for multiple service levels networks on chip. In Proceedings of ASYNC'05, pages 44–53, 2005.

[92 — Borrione:2007:GMF]

Laurence Pierre Dominique Borrione, Amr Helmy and Julien Schmaltz. A generic model for formally verifying NoC communication architectures: A case study. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

[93 — Dumitras:2003:OCS]

Tudor Dumitras and Radu Marculescu. On-Chip Stochastic Communication. In Proc. Design Automation and Test in Europe (DATE), March 2003.

[94 — Dumitras:2003:TOC]

T. Dumitras, S. Kerner, and R. Marculescu. Towards on-chip fault-tolerant communication. In Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2003.

[95 — Dumitrascu:2006:FMP]

F Dumitrascu, I Bacivarov, L Pieralisi, M Bonaciu, and A Jerraya. Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. In In Proc. Design, Automation and Test in Europe (DATE), March 2006.

[96 — Eisley:2004:HLP]

Noel Eisley and Li-Shiuan Peh. High-level power analysis for on-chip networks. In Proceedings of CASES, pages 104–115. ACM Press, 2004.

[97 — Eisley:2006:INC]

Noel Eisley, Li-Shiuan Peh, and Li-Shang. In-network cache coherence. In Proc. of the 39th Annual Intl. Symp. on Microarchitecture (MICRO), 2006.

[98 — Essakimuthu:2002:AAP]

G. Essakimuthu, N. Vijaykrishnan, and M. J. Irwin. An analytical power estimation model for crossbar interconnects. In IEEE International ASIC/SOC Conference, September 25-28 2002.

[99 — Fairbanks:2002:TDC]

Scott Fairbanks and Simon Moore. The Distributed Clock Generator. In Proc. of the second ACiD-WG Workshop, Munich, Germany, January 2002.

[100 — Fairbanks:2005:STC]

Scott Fairbanks and Simon Moore. Self-timed circuitry for global clocking. In Proceedings of the 11th International Symposium on Asynchronous Circuits and Systems, 2005.

[101 — Felicijan:2003:AAT]

T. Felicijan and S. B. Furber. An asynchronous ternary logic signaling system. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(6):1114–1119, December 2003.

[102 — Felicijan:2003:AAL]

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